82801CA Datasheet, PDF (414/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

AC ’97 Audio Controller Registers (D31:F5)
13.1.2
13.1.3
DID—Device Identification Register (Audio—D31:F5)
Offset:
Default Value:
Lockable:
02–03h
2485h
No
Attribute:
Size:
Power Well:
RO
16 Bits
Core
Bit
15:0 Device Identification Value.
Description
PCICMD—PCI Command Register (Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
04–05h
0000h
No
Attribute:
Size:
Power Well:
R/W
16 bits
Core
PCICMD is a 16-bit control register. Refer to the PCI 2.2 specification for complete details on each
bit.
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Description
Reserved. Read 0.
Fast Back to Back Enable (FBE). Not implemented. Hardwired to 0.
SERR# Enable (SERR_EN). Not implemented. Hardwired to 0.
Wait Cycle Control (WCC). Not implemented. Hardwired to 0.
Parity Error Response (PER). Not implemented. Hardwired to 0.
VGA Palette Snoop (VPS). Not implemented. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE). Not implemented. Hardwired to 0.
Special Cycle Enable (SCE). Not implemented. Hardwired to 0.
Bus Master Enable (BME)—R/W. Controls standard PCI bus mastering capabilities.
0 = Disable.
1 = Enable.
Memory Space Enable (MSE). Hardwired to 0, AC ’97 does not respond to memory accesses
I/O Space Enable (IOE)—R/W. This bit controls access to the AC ’97 Audio Controller I/O space
registers.
0 = Disable (Default).
1 = Enable access to I/O space. The Native PCI Mode Base Address register should be
programmed prior to setting this bit.
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Intel^® 82801CA ICH3-S Datasheet