82801CA Datasheet, PDF (340/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.8.3.3
9.8.3.4
PM1_CNT—Power Management 1 Control Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 04h
(ACPI PM1a_CNT_BLK)
0000h
No
Bits 0–7: Core,
Bits 8–15: Resume
Attribute:
Size:
Usage:
R/W
32-bit
ACPI or Legacy
Bit
15:14
13
12:10
9:3
2
1
0
Description
Reserved.
Sleep Enable (SLP_EN)—WO.
Setting this bit causes the system to sequence into the Sleep state defined by the SLP_TYP field.
Sleep Type (SLP_TYP)—R/W. This 3-bit field defines the type of Sleep the system should enter
when the SLP_EN bit is set to 1.
000 = ON: Typically maps to S0 state.
001 = Asserts STPCLK#. Puts processor in Stop-Grant state. Optional to assert CPUSLP# to put
the processor in sleep state: Typically maps to S1 state.
010 = Reserved.
011 = Reserved.
100 = Reserved.
101 = Suspend-To-RAM. Assert SLP_S1# and SLP_S3#: Typically maps to S3 state.
110 = Suspend-To-Disk. Assert SLP_S1#, SLP_S3#, and SLP_S5# SLP_S3# and SLP_S5#:
Typically maps to S4 state.
111 = Soft Off. Assert SLP_S1#, SLP_S3#, and SLP_S5# SLP_S3#, and SLP_S5#: Typically
maps to S5 state.
Reserved.
Global Release (GBL_RLS)—WO.
0 = This bit always reads as 0.
1 = ACPI software writes a 1 to this bit to raise an event to the BIOS. BIOS software has a
corresponding enable and status bits to control its ability to receive ACPI events.
Reserved.
SCI Enable (SCI_EN)—R/W. Selects the SCI interrupt or the SMI# interrupt for various events
including the bits in the PM1_STS register (bit 10, 8, 0), and bits in GPE0_STS.
0 = These events will generate an SMI#.
1 = These events will generate an SCI.
PM1_TMR—Power Management 1 Timer Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 08h
(ACPI PMTMR_BLK)
xx000000h
No
Core
Attribute:
Size:
Usage:
RO
32-bit
ACPI
Bit
Description
31:24
23:0
Reserved.
Timer Value (TMR_VAL)—RO. Returns the running count of the PM timer. This counter runs off a
3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to zero during a PCI reset, and then
continues counting as long as the system is in the S0 state.
Anytime bit 22 of the timer goes HIGH to LOW (bits referenced from 0 to 23), the TMROF_STS bit is
set. The High-to-Low transition will occur every 2.3435 seconds. If the TMROF_EN bit is set, an SCI
interrupt is also generated.
340
Intel^® 82801CA ICH3-S Datasheet