82801CA Datasheet, PDF (161/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.14.2
5.14.3
5.14.4
Power Wells
Some GPIOs exist in the resume power plane. Care must be taken to make sure GPIO signals are
not driven high into powered-down planes.
Some ICH3 GPIOs may be connected to pins on devices that exist in the core well. If these GPIOs
are outputs, there is a danger that a loss of core power (PWROK low) or a Power Button Override
event will result in the ICH3 driving a pin to a logic “1” to another device that is powered down.
SMI# and SCI Routing
The routing bits for GPIO[0:15] allow an input to be routed to SMI# or SCI, or neither. Note that a
bit can be routed to either an SMI# or an SCI, but not both.
Power Wells
GPIO[1:15] have “sticky” bits on the input. Refer to the GPE1_STS Register. As long as the signal
goes active for at least 2 clocks, the ICH3 will keep the sticky status bit active. The active level can
be selected in the GP_LVL Register.
If the system is in an S0 or an S1-D state, the GPI inputs are sampled at 33 MHz, so the signal only
needs to be active for about 60 ns to be latched. In the S1-M or S3–S5 states, the GPI inputs are
sampled at 32.768 kHz, and thus must be active for at least 61 microseconds to be latched.
If the input signal is still active when the latch is cleared, it will again be set. Another edge trigger
is not required. This makes these signals “level” triggered inputs.
5.15
IDE Controller (D31:F1)
The ICH3 IDE controller features two sets of interface signals (Primary and Secondary) that can be
independently enabled, tri-stated or driven low.
The ICH3 IDE controller supports both legacy mode and native mode IDE interface. In native
mode, the IDE controller is a fully PCI compliant software interface and does not use any legacy
I/O or interrupt resources.
The IDE interfaces of the ICH3 can support several types of data transfers:
• Programmed I/O (PIO): Processor is in control of the data transfer.
• Intel 8237 style DMA: DMA protocol that resembles the DMA on the ISA bus, although it
does not use the 8237 in the ICH3. This protocol off loads the processor from moving data.
This allows higher transfer rate of up to 16 MB/s.
• Ultra ATA/33: DMA protocol that redefines signals on the IDE cable to allow both host and
target throttling of data and transfer rates of up to 33 MB/s.
• Ultra ATA/66: DMA protocol that redefines signals on the IDE cable to allow both host and
target throttling of data and transfer rates of up to 66 MB/s.
• Ultra ATA/100: DMA protocol that redefines signals on the IDE cable to allow both host and
target throttling of data and transfer rates of up to 100 MB/s.
Intel^® 82801CA ICH3-S Datasheet
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