82801CA Datasheet, PDF (92/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
Figure 5-9. Intel^® ICH3 DMA Controller
Channel 0
Channel 1
Channel 2
Channel 3
DMA-1
Channel 4
Channel 5
Channel 6
Channel 7
DMA-2
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Each DMA channel is hardwired to the compatible settings for DMA device size: channels [3:0]
are hardwired to 8-bit, count-by-bytes transfers; channels [7:5] are hardwired to 16-bit, count-by-
words (address shifted) transfers.
ICH3 provides 24-bit addressing in compliance with the ISA-Compatible specification. Each
channel includes a 16-bit ISA-compatible current register which holds the 16 least-significant bits
of the 24-bit address, an ISA-compatible page register which contains the eight next most
significant bits of address.
The DMA controller also features refresh address generation, and autoinitialization following a
DMA termination.
5.4.1
5.4.1.1
Channel Priority
For priority resolution, the DMA consists of two logical channel groups: channels 0–3 and
channels 4–7. Each group may be in either fixed or rotate mode, as determined by the DMA
Command Register.
DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service. However, a
software request for DMA service can be presented through each channel's DMA request register.
A software request is subject to the same prioritization as any hardware request. Please see the
detailed register description for request register programming information in the DMA register
description section.
Fixed Priority
The initial fixed priority structure is as follows:
High priority
Low priority
(0, 1, 2, 3)
(5, 6, 7)
The fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. In this scheme, Channel 0 has the highest
priority, and channel 7 has the lowest priority. Channels [3:0] of DMA-1 assume the priority
position of Channel 4 in DMA-2, thus taking priority over channels 5, 6, and 7.
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Intel^® 82801CA ICH3-S Datasheet