82801CA Datasheet, PDF (7/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

5.5 PCI DMA ........................................................................................................95
5.5.1 PCI DMA Expansion Protocol ...........................................................95
5.5.2 PCI DMA Expansion Cycles .............................................................97
5.5.3 DMA Addresses ................................................................................97
5.5.4 DMA Data Generation.......................................................................97
5.5.5 DMA Byte Enable Generation...........................................................98
5.5.6 DMA Cycle Termination ....................................................................98
5.5.7 LPC DMA ..........................................................................................98
5.5.8 Asserting DMA Requests..................................................................99
5.5.9 Abandoning DMA Requests..............................................................99
5.5.10 General Flow of DMA Transfers .....................................................100
5.5.11 Terminal Count ...............................................................................100
5.5.12 Verify Mode.....................................................................................100
5.5.13 DMA Request Deassertion .............................................................101
5.5.14 SYNC field / LDRQ# Rules .............................................................102
5.6 Intel^® 8254 Timers (D31:F0) ........................................................................102
5.6.1 Counter 0, System Timer ................................................................102
5.6.2 Counter 1, Refresh Request Signal ................................................102
5.6.3 Counter 2, Speaker Tone................................................................103
5.6.4 Timer Programming ........................................................................103
5.6.5 Reading from the Interval Timer .....................................................104
5.6.5.1 Simple Read ....................................................................104
5.6.5.2 Counter Latch Command ................................................105
5.6.5.3 Read Back Command .....................................................105
5.7 Intel^® 8259 Interrupt Controllers (PIC) (D31:F0)..........................................106
5.7.1 Interrupt Handling ...........................................................................107
5.7.1.1 Generating Interrupts.......................................................107
5.7.1.2 Acknowledging Interrupts ................................................107
5.7.1.3 Hardware/Software Interrupt Sequence ..........................108
5.7.2 Initialization Command Words (ICWx) ............................................108
5.7.3 Operation Command Words (OCW) ...............................................109
5.7.4 Modes of Operation ........................................................................109
5.7.4.1 Fully Nested Mode...........................................................109
5.7.4.2 Special Fully Nested Mode..............................................110
5.7.4.3 Automatic Rotation Mode (Equal Priority Devices)..........110
5.7.4.4 Specific Rotation Mode (Specific Priority) .......................110
5.7.4.5 Poll Mode.........................................................................110
5.7.4.6 Cascade Mode ................................................................111
5.7.4.7 Edge and Level Triggered Mode .....................................111
5.7.4.8 End of Interrupt Operations .............................................111
5.7.4.9 Normal End of Interrupt ...................................................111
5.7.4.10 Automatic End of Interrupt Mode.....................................111
5.7.5 Masking Interrupts ..........................................................................112
5.7.5.1 Masking on an Individual Interrupt Request ....................112
5.7.5.2 Special Mask Mode .........................................................112
5.7.6 Steering PCI Interrupts ...................................................................112
5.8 Advanced Interrupt Controller (APIC) (D31:F0) ...........................................113
5.8.1 Interrupt Handling ...........................................................................113
5.8.2 Interrupt Mapping............................................................................114
5.8.3 APIC Bus Functional Description....................................................115
5.8.3.1 Physical Characteristics of APIC .....................................115
5.8.3.2 APIC Bus Arbitration........................................................115
5.8.3.3 Bus Message Formats.....................................................116
Intel^® 82801CA ICH3-S Datasheet
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