82801CA Datasheet, PDF (250/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LAN Controller Registers (B1:D8:F0)
Table 7-5. Self-Test Results Format
Bit
31:13
12
11:6
5
4
3
2
1:0
Description
Reserved.
General Self-Test Result.
0 = Pass
1 = Fail
Reserved.
Diagnose Result. This bit provides the result of an internal diagnostic test of the Serial Subsystem.
0 = Pass
1 = Fail
Reserved.
Register Result. This bit provides the result of a test of the internal Parallel Subsystem registers.
0 = Pass
1 = Fail
ROM Content Result. This bit provides the result of a test of the internal microcode ROM.
0 = Pass
1 = Fail
Reserved.
7.2.5
EEPROM Control Register
Offset Address: 0Eh
Default Value: 00h
Attribute:
Size:
RO/R/W
8 bits
The EEPROM Control Register is a 16-bit field that enables a read from and a write to the external
EEPROM.
Bit
Description
7:4 Reserved.
EEPROM Serial Data Out (EEDO)—RO. Note that this bit represents “Data Out” from the
3 perspective of the EEPROM device. This bit contains the value read from the EEPROM when
performing read operations.
EEPROM Serial Data In (EEDI)—WO. Note that this bit represents “Data In” from the perspective of
2 the EEPROM device. The value of this bit is written to the EEPROM when performing write
operations.
EEPROM Chip Select (EECS)—R/W.
1
0 = Drives the ICH3’s EE_CS signal low, to disable the EEPROM. this bit must be set to 0 for a
minimum of 1µs between consecutive instruction cycles.
1 = Drives the ICH3’s EE_CS signal high, to enable the EEPROM.
EEPROM Serial Clock (EESK)—R/W. Toggling this bit, clocks data into or out of the EEPROM.
Software must ensure that this bit is toggled at a rate that meets the EEPROM component’s
0 ^{minimum clock frequency specification.}
0 = Drives the ICH3’s EE_SHCLK signal low.
1 = Drives the ICH3’s EE_SHCLK signal high.
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Intel^® 82801CA ICH3-S Datasheet