82801CA Datasheet, PDF (237/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LAN Controller Registers (B1:D8:F0)
7.1.4
7.1.5
PCISTS—PCI Status Register (LAN Controller—B1:D8:F0)
Offset Address: 06–07h
Default Value: 0290h
Attribute:
Size:
RO, R/WC
16 bits
Bit
Description
Detected Parity Error (DPE)—R/WC.
15 ^{0 = This bit is cleared by writing a 1 to the bit location.}
1 = The ICH3’s integrated LAN Controller has detected a parity error on the PCI bus (will be set
even if Parity Error Response is disabled in the PCI Command register).
Signaled System Error (SSE)—R/WC.
14 ^{0 = This bit is cleared by writing a 1 to the bit location.}
1 = The ICH3’s integrated LAN Controller has asserted SERR#. (SERR# can be routed to cause
NMI, SMI# or interrupt.
Master Abort Status (MAS)—R/C.
13 _{0 = This bit is cleared by writing a 1 to the bit location.}
1 = The ICH3’s integrated LAN Controller (as a PCI master) has generated a master abort.
Received Target Abort (RTA)—R/WC.
12 _{0 = This bit is cleared by writing a 1 to the bit location.}
1 = The ICH3’s integrated LAN Controller (as a PCI master) has received a target abort.
11 Signaled Target Abort (STA)—RO. Hardwired to 0. The device will never signal Target Abort.
DEVSEL# Timing Status (DEV_STS)—RO.
10:9
01h = Medium timing.
Data Parity Error Detected (DPED)—R/WC.
0 = This bit is cleared by writing a 1 to the bit location.
8
1 = All of the following three conditions have been met:
1. The LAN Controller is acting as bus master.
2. The LAN Controller has asserted PERR# (for reads) or detected PERR# asserted (for writes).
3. The Parity Error Response bit in the LAN Controller’s PCI Command Register is set.
7
Fast Back to Back (FB2B)—RO. Hardwired to 1. The device can accept fast back-to-back
transactions.
6 User Definable Features (UDF)—RO. Hardwired to 0. Not implemented.
5 66 MHz Capable (66MHZ_CAP)—RO. Hardwired to 0. The device does not support 66 MHz PCI.
Capabilities List (CAP_LIST)—RO.
4
0 = The EEPROM indicates that the integrated LAN controller does not support PCI Power
Management.
1 = The EEPROM indicates that the integrated LAN controller supports PCI Power Management.
3:0 Reserved.
REVID—Revision ID Register (LAN Controller—B1:D8:F0)
Offset Address: 08h
Default Value: See Note 1
Attribute:
Size:
RO
8 bits
Bit
Description
Revision Identification Value. 8-bit value that indicates the revision number for the integrated LAN
7:0 Controller. The three least significant bits in this register may be overridden by the ID and REV ID
fields in the EEPROM.
NOTE 1: Refer to the Specification Update for the Revision ID.
Intel^® 82801CA ICH3-S Datasheet
237