82801CA Datasheet, PDF (315/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.4.11
ELCR2—Slave Controller Edge/Level Triggered Register
Offset Address: 4D1h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode
(bit[x] = 1), the interrupt is recognized by a high level. The real time clock interrupt (IRQ8#) and
the floating point error interrupt (IRQ13) cannot be programmed for level mode.
Bit
IRQ15 ECL—R/W.
7 _{0 = Edge.}
1 = Level.
IRQ14 ECL—R/W.
6 _{0 = Edge.}
1 = Level.
5 Reserved. Must be 0.
IRQ12 ECL—R/W.
4 _{0 = Edge.}
1 = Level.
IRQ11 ECL—R/W.
3 _{0 = Edge.}
1 = Level.
IRQ10 ECL—R/W.
2 _{0 = Edge.}
1 = Level.
IRQ9 ECL—R/W.
1 _{0 = Edge.}
1 = Level.
0 Reserved. Must be 0.
Description
Intel^® 82801CA ICH3-S Datasheet
315