82801CA Datasheet, PDF (144/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
Table 5-41. Causes of Wake Events
Cause
RTC Alarm
Power Button
GPI[0:n]
USB
LAN
RI#
AC ’97
Primary PME#
Secondary PME#
SMBALERT#
SMBus Slave Message
SMBus Host Notify Message
Received
States Can
Wake From
S1–S5
(Note 1)
S1–S5
S1–S5
(Note 1)
S1–S4
S1–S5
S1–S5
(Note 1)
S1–S5
S1–S5
S1–S5
(Note 1)
S1–S4
S1–S5
S1–S5
How Enabled
Set RTC_EN bit in PM1_EN Register
Always enabled as Wake event
GPE1_EN Register
Set USB1_EN, USB 2_EN or USB3_EN bits in GPE0_EN
Register
Will use PME#. Wake enable set with LAN logic.
Set RI_EN bit in GPE0_EN Register
Set AC97_EN bit in GPE0_EN Register
PME_B0_EN bit in GPE0_EN Register
Set PME_EN bit in GPE0_EN Register.
SMB_WAK_EN in the GPE0 Register
Wake/SMI# command always enabled as a Wake Event.
Note:SMBus Slave Message can wake the system from
S1–S5, as well as from S5 due to Power Button
Override.
HOST_NOTIFY_WKEN bit SMBus Slave Command
Register. Reported in the SMB_WAK_STS bit in the
GPEO_STS Register.
NOTES:
1. This will be a wake event from S5 only if the sleep state was entered by setting the SLP_EN and SLP_TYP
bits via software.
2. If in the S5 state due to a powerbutton override, the possible wake events are due to Power Button, Hard
Reset Without Cycling (See Command Type 3 in Table 5-93), and Hard Reset System (See Command Type
4 in Table 5-93).
It is important to understand that the various GPIs have different levels of functionality when used
as wake events. The GPIs that reside in the core power well can only generate wake events from an
S1 state. Also only certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits
reside in ACPI I/O space. Table 5-42 summarizes the use of GPIs as wake events.
Table 5-42. GPI Wake Events
GPI
GPI[7:0], GPI[23:16]
GPI[15:8]
Power Well
Core
Resume
Wake From
S1
S1–S5
Notes
ACPI Compliant
The latency to exit the various Sleep states varies greatly and is heavily dependent on power supply
design, so much so that the exit latencies due to the ICH3 are insignificant.
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Intel^® 82801CA ICH3-S Datasheet