82801CA Datasheet, PDF (409/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

SMBus Controller Registers (D31:F3)
12.2.10
.
SLV_DATA—Receive Slave Data Register
Register Offset: 0Ah
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
RO
16 bits
Resume
This register contains the 16-bit data value written by the external SMBus master. The processor
can then read the value from this register. This register is reset by RSMRST#, but not PCIRST#
Bit
15:8
7:0
Description
Data Message Byte 1 (DATA_MSG1)—RO. See Section 5.17.6 for a discussion of this field.
Data Message Byte 0 (DATA_MSG0)—RO. See Section 5.17.6 for a discussion of this field.
12.2.11 SMLINK_PIN_CTL—SMLink Pin Control Register
Register Offset: 0Eh
Default Value: See below
Attribute:
Size:
R/W
8 bits
Note: This register is in the resume well and is reset by RSMRST#
Bit
Description
7:3 Reserved.
SMLINK_CLK_CTL—R/W. This Read/Write bit has a default of 1.
2 ^{0 = ICH3 will drive the SMLINK[0] pin low, independent of what the other SMLINK logic would}
otherwise indicate for the SMLINK[0] pin.
1 = The SMLINK[0] pin is Not overdriven low. The other SMLINK logic controls the state of the pin.
SMLINK[1]_CUR_STS—R/W. This read-only bit has a default value that is dependent on an external
1 signal level. This pin returns the value on the SMLINK[1] pin. It will be 1 to indicate high, 0 to indicate
low. This allows software to read the current state of the pin.
SMLINK[0]_CUR_STS—R/W. This read-only bit has a default value that is dependent on an external
0 signal level. This pin returns the value on the SMLINK[0] pin. It will be 1 to indicate high, 0 to indicate
low. This allows software to read the current state of the pin.
12.2.12 SMBUS_PIN_CTL—SMBus Pin Control Register
Register Offset: 0Fh
Default Value: See below
Attribute:
Size:
R/W
8 bits
Note: This register is in the resume well and is reset by RSMRST#.
Bit
Description
7:3 Reserved.
SMBCLK_CTL—R/W. This Read/Write bit has a default of 1.
2 ^{0 = ICH3 will drive the SMBCLK pin low, independent of what the other SMB logic would otherwise}
indicate for the SMBCLK pin.
1 = The SMBCLK pin is Not overdriven low. The other SMBus logic controls the state of the pin.
SMBDATA_CUR_STS—R/W. This read-only bit has a default value that is dependent on an external
1 signal level. This pin returns the value on the SMBDATA pin. It will be 1 to indicate high, 0 to indicate
low. This allows software to read the current state of the pin.
SMBCLK_CUR_STS—R/W. This read-only bit has a default value that is dependent on an external
0 signal level. This pin returns the value on the SMBCLK pin. It will be 1 to indicate high, 0 to indicate
low. This allows software to read the current state of the pin.
Intel^® 82801CA ICH3-S Datasheet
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