82801CA Datasheet, PDF (90/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
Abort Mechanism
When performing an Abort, the ICH3 drives LFRAME# active for four consecutive clocks. On the
fourth clock, it drives LAD[3:0] to 1111b.
Figure 5-8. Abort Mechanism
LCLK
LFRAME#
LAD[3:0]
Start
ADDR
C YC T YPE
D ir & Size
TAR _Sync
Peripheral m ust
stop driving
Too many
Syncs causes
tim eout
Chipset will
drive high
The ICH3 performs an abort for the following cases (possible failure cases):
• ICH3 starts a memory, I/O, or DMA cycle, but no device drives a valid SYNC after four
consecutive clocks.
• ICH3 starts a memory, I/O, or DMA cycle, and the peripheral drives an invalid SYNC pattern.
• A peripheral drives an illegal address when performing bus master cycles.
• A peripheral drives an invalid value.
5.3.1.9 I/O Cycles
For I/O cycles targeting registers specified in the ICH3’s decode ranges, the ICH3 performs I/O
cycles as defined in the LPC specification. These will be 8-bit transfers. If the processor attempts a
16-bit or 32-bit transfer, the ICH3 breaks the cycle up into multiple 8-bit transfers to consecutive
I/O addresses.
Note: If the cycle is not claimed by any peripheral (and subsequently aborted), the ICH3 returns a value
of all 1s (FFh) to the processor. This is to maintain compatibility with ISA I/O cycles where pull-up
resistors would keep the bus high if no device responds.
5.3.1.10 Bus Master Cycles
The ICH3 supports Bus Master cycles and requests (using LDRQ#) as defined in the LPC
specification. The ICH3 has two LDRQ# inputs, and thus supports two separate bus master
devices. It uses the associated START fields for Bus Master 0 (0010b) or Bus Master 1 (0011b).
Note: The ICH3 does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters should only
perform memory read or memory write cycles.
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Intel^® 82801CA ICH3-S Datasheet