82801CA Datasheet, PDF (229/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Register and Memory Mapping
Table 6-2 lists the Intel ICH3 Device IDs. Refer to the Specification Update for the Revision IDs.
Table 6-2. Intel^® ICH3 Device IDs
Device
Function
Description
D30, F0
D31, F0
D31, F1
D31, F3
D31, F5
D31, F6
D8, F0
D29, F0
D29, F1
D29, F2
P2P Bridge
P2L Bridge
IDE
SMBus
AC97 Audio
AC97 Modem
LAN
USBC #1
USBC #2
USBC #3
ICH3 Dev ID
244Eh
2480h
248Bh
2483h
2485h
2486h
Note 1
2482h
2484h
2487h
Comments
6.2 PCI Configuration Map
Each PCI function on the ICH3 has a set of PCI configuration registers. The register address map
tables for these register sets are included at the beginning of the chapter for the particular function.
Refer to Table A-1 for a complete list of all PCI Configuration Registers.
Configuration Space registers are accessed through configuration cycles on the PCI bus by the
Host bridge using configuration mechanism #1 detailed in the PCI Local Bus Specification,
Revision 2.2.
Some of the PCI registers contain reserved bits. Software must deal correctly with fields that are
reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on
reserved bits being any particular value. On writes, software must ensure that the values of
reserved bit positions are preserved. That is, the values of reserved bit positions must first be read,
merged with the new values for other bit positions and then written back. Note the software does
not need to perform read, merge, write operation for the configuration address register.
In addition to reserved bits within a register, the configuration space contains reserved locations.
Software should not write to reserved PCI configuration locations in the device-specific region
(above address offset 3Fh).
Intel^® 82801CA ICH3-S Datasheet
229