82801CA Datasheet, PDF (259/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Hub Interface to PCI Bridge Registers (D30:F0)
Hub Interface to PCI Bridge Registers
(D30:F0)
8
The hub interface to PCI Bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the
ICH3 implements the buffering and control logic between PCI and the hub interface. The
arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must
decode the ranges for the hub interface. All register contents will be lost when core well power is
removed.
8.1
PCI Configuration Registers (D30:F0)
Note: Registers that are not shown should be treated as Reserved (See Section 6.2 for details).
.
Table 8-1. PCI Configuration Map (HUB-PCI—D30:F0)
Offset
00–01h
02–03h
04–05h
06–07h
08h
0Ah
0Bh
0Dh
0Eh
18h
19h
1Ah
1Bh
1Ch
1Dh
1E–1Fh
20–21h
22–23h
24–25h
26–27h
30–31h
32–33h
3Ch
3E–3Fh
Mnemonic
VID
DID
CMD
PD_STS
REVID
SCC
BCC
PMLT
HEADTYP
PBUS_NUM
SBUS_NUM
SUB_BUS_NUM
SMLT
IOBASE
IOLIM
SECSTS
MEMBASE
MEMLIM
PREF_MEM_BASE
PREF_MEM_MLT
IOBASE_HI
IOLIMIT_HI
INT_LINE
BRIDGE_CNT
Register Name/Function
Vendor ID
Device ID
PCI Device Command
PCI Device Status
Revision ID
Sub Class Code
Base Class Code
Primary Master Latency Timer
Header Type
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Secondary Master Latency Timer
I/O Base Register
I/O Limit Register
Secondary Status
Memory Base
Memory Limit
Prefetchable Memory Base
Prefetchable Memory Limit
I/O Base Upper 16 Bits
I/O Limit Upper 16 Bits
Interrupt Line
Bridge Control
Default
8086h
244Eh
0001h
0080h
See Note
04h
06h
00h
01h
00h
00h
00h
00h
F0h
00h
0280h
FFF0h
0000h
0000h
0000h
0000h
0000h
00h
0000h
Type
RO
RO
R/W
R/W
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
R/W
Intel^® 82801CA ICH3-S Datasheet
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