82801CA Datasheet, PDF (137/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.12.3 System Power Planes
The system has several independent power planes, as described in Table 5-37. Note that when a
particular power plane is shut off, it should go to a 0 V level.
s
Table 5-37. System Power Plane
Plane
Processor
Main
Memory
Device[n]
Controlled
By
SLP_S3#
Signal
SLP_S3#
Signal
SLP_S5#
Signal
GPIO
Description
SLP_S1# puts the clock generator into a low-power state, but does not cut
the power to the processor. The SLP_S3# signal can be used to cut the
processor’s power completely
When SLP_S3# goes active, power can be shut off to any circuit not
required to wake the system from the S3 state. Since the S3 state requires
that the memory context be preserved, power must be retained to the main
memory.
The processor, devices on the PCI bus, LPC I/F downstream hub interface
and AGP will typically be shut off when the Main power plane is shut,
although there may be small subsections powered.
When the SLP_S5# goes active, power can be shut off to any circuit not
required to wake the system from the S4 or S5 state. Since the memory
context does not need to be preserved in the S5 state, the power to the
memory can also be shut down.
Individual subsystems may have their own power plane. For example, GPIO
signals may be used to control the power to disk drives, audio amplifiers, or
the display screen.
5.12.4 Intel^® ICH3 Power Planes
The ICH3 power planes were previously defined in Section 3.1.
Although not specific power planes within the ICH3, there are many interface signals that go to
devices that may be powered down. These include:
• IDE: ICH3 can tri-state or drive low all IDE output signals and shut off input buffers.
• USB:
ICH3 can tri-state USB output signals and shut off input buffers if USB wakeup is
not desired
• AC ’97: ICH3 can drive low the outputs and shut off inputs
5.12.5
SMI#/SCI Generation
Upon any SMI# event taking place, ICH3 will assert SMI# to the processor, which will cause it to
enter SMM space. SMI# remains active until the EOS bit is set. When the EOS bit is set, SMI# will
go inactive for a minimum of 4 PCICLK. If another SMI event occurs, SMI# will be driven active
again.
The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating system. In
non-APIC systems (which is the default), the SCI IRQ is routed to one of the 8259 interrupts
(IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed to level mode for that
interrupt.
Intel^® 82801CA ICH3-S Datasheet
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