82801CA Datasheet, PDF (376/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

IDE Controller Registers (D31:F1)
10.1.24
IDE_CONFIG—IDE I/O Configuration Register
Address Offset: 54h
Default Value: 00h
Attribute:
Size:
R/W
32 bits
Bit
31:20
19:18
17:16
15
14
13
12
11
10
9:8
7
6
5
4
3
2
Description
Reserved.
SEC_SIG_MODE—R/W. These bits should always be set to 00b.
00 = Normal (Enabled)
01 = Reserved
10 = Reserved
11 = Reserved
PRIM_SIG_MODE—R/W. These bits should always be set to 00b.
00 = Normal (Enabled)
01 = Reserved
10 = Reserved
11 = Reserved
Fast Secondary Drive 1 Base Clock (FAST_SCB1)—R/W. This bit is used in conjunction with the
SCT1 bits to enable/disable Ultra ATA/100 timings for the Secondary Slave drive.
0 = Disable Ultra ATA/100 timing for the Secondary Slave drive.
1 = Enable Ultra ATA/100 timing for the Secondary Slave drive (overrides bit 3 in this register).
Fast Secondary Drive 0 Base Clock (FAST_SCB0)—R/W. This bit is used in conjunction with the
SCT0 bits to enable/disable Ultra ATA/100 timings for the Secondary Master drive.
0 = Disable Ultra ATA/100 timing for the Secondary Master drive.
1 = Enable Ultra ATA/100 timing for the Secondary Master drive (overrides bit 2 in this register).
Fast Primary Drive 1 Base Clock (FAST_PCB1)—R/W. This bit is used in conjunction with the
PCT1 bits to enable/disable Ultra ATA/100 timings for the Primary Slave drive.
0 = Disable Ultra ATA/100 timing for the Primary Slave drive.
1 = Enable Ultra ATA/100 timing for the Primary Slave drive (overrides bit 1 in this register).
Fast Primary Drive 0 Base Clock (FAST_PCB0)—R/W. This bit is used in conjunction with the
PCT0 bits to enable/disable Ultra ATA/100 timings for the Primary Master drive.
0 = Disable Ultra ATA/100 timing for the Primary Master drive.
1 = Enable Ultra ATA/100 timing for the Primary Master drive (overrides bit 0 in this register).
Reserved.
WR_PingPong_EN—R/W.
0 = Disabled. The buffer will behave similar to PIIX4.
1 = Enables the write buffer to be used in a split (ping/pong) manner.
Reserved.
Secondary Slave Channel Cable Reporting—R/W. BIOS should program this bit to tell the IDE
driver which cable is plugged into the channel.
0 = 40 conductor cable is present.
1 = 80 conductor cable is present.
Secondary Master Channel Cable Reporting—R/W. Same description as bit 7.
Primary Slave Channel Cable Reporting—R/W. Same description as bit 7.
Primary Master Channel Cable Reporting—R/W. Same description as bit 7.
Secondary Drive 1 Base Clock (SCB1)—R/W.
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings.
Secondary Drive 0 Base Clock (SCBO)—R/W.
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings.
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Intel^® 82801CA ICH3-S Datasheet