82801CA Datasheet, PDF (278/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.1.4
9.1.5
PCISTA—PCI Device Status Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
06–07h
0280h
No
Attribute:
Size:
Power Well:
R/WC
16-bit
Core
Bit
Description
Detected Parity Error (DPE)— R/W.
15 _{0 = This bit is cleared by software writing a 1 to the bit position.}
1 = PERR# signal goes active. Set even if the PER bit is 0.
Signaled System Error (SSE)—R/W.
0 = This bit is cleared by software writing a 1 to the bit position.
14 _{1 = Set by the ICH3 if the SERR_EN bit is set and the ICH3 generates an SERR# on function 0. The}
ERR_STS register can be read to determine the cause of the SERR#. The SERR# can be routed
to cause SMI#, NMI, or interrupt.
Master Abort Status (MAS)—R/W.
13 _{0 = This bit is cleared by software writing a 1 to the bit position.}
1 = ICH3 generated a master abort on PCI due to LPC I/F master or DMA cycles.
Received Target Abort (RTA)—R/W.
12 _{0 = This bit is cleared by software writing a 1 to the bit position.}
1 = ICH3 received a target abort during LPC I/F master or DMA cycles to PCI.
Signaled Target Abort (STA)—R/W.
11 ^{This bit is cleared by software writing a 1 to the bit position.}
1 = ICH3 generated a target abort condition on PCI cycles claimed by the ICH3 for ICH3 internal
registers or for going to LPC I/F.
DEVSEL# Timing Status (DEV_STS)—RO.
10:9
01 = Medium Timing.
Data Parity Error Detected (DPED)—R/WC.
0 = This bit is cleared by software writing a 1 to the bit position.
8 ^{1 = Set when all three of the following conditions are true:}
- The ICH3 is the initiator of the cycle,
- The ICH3 asserted PERR# (for reads) or observed PERR# (for writes), and
- The PER bit is set.
7
Fast Back to Back (FB2B)—RO. Always 1. Indicates ICH3 as a target can accept fast back-to-back
transactions.
6 User Definable Features (UDF). Hardwired to 0.
5 66 MHz Capable (66MHZ_CAP)—RO. Hardwired to 0.
4:0 Reserved.
REVID—Revision ID Register (LPC I/F—D31:F0)
Offset Address: 08h
Default Value: See Note
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Revision Identification Value—RO. 8-bit value that indicates the revision number for the LPC bridge.
NOTE: Refer to the Specification Update for the Revision ID.
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Intel^® 82801CA ICH3-S Datasheet