82801CA Datasheet, PDF (344/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.8.3.8 GPE0_EN—General Purpose Event 0 Enables Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 2Ah
(ACPI GPE0_BLK + 2)
0000h
No
Bits 0–7 Resume,
Bits 8–15 RTC
Attribute:
Size:
Usage:
R/W
16-bit
ACPI
Note: This register is symmetrical to the General Purpose Event 0 Status Register. All the bits in this
register should be cleared to 0 based on a Power Button Override. The resume well bits are all
cleared by RSMRST#. The RTC sell bits are cleared by RTCRST#.
Bit
15:14
13
12
11
10:9
8
7
6
5
4
3
2
1
0
Description
Reserved.
PME_B0_EN—R/W. Enables the setting of the PME_B0_STS bit to generate a wake event and/
or an SCI or SMI#. PME_B0_STS can be a wake event from the S1–S4 states, or from S5 (if
entered via SLP_TYP and SLP_EN) or power failure, but not Power Button Override. This bit
defaults to 0. It is only cleared by Software or RTCRST#. It is not cleared by CF9h writes.
USB3_EN—R/W.
0 = Disable.
1 = Enable the setting of the USB3_STS bit to generate a wake event. The USB3_STS bit is set
when USB 1.1 Controller #3 signals a wake event. Break events are handled via the USB
interrupt.
PME_EN—R/W.
0 = Disable.
1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI. PME# can be
a wake event from the S1–S4 state or from S5 (if entered via SLP_EN, but not power button
override).
Reserved.
RI_EN—R/W. The value of this bit will be maintained through a G3 state and is not affected by a
hard reset caused by a CF9h write.
0 = Disable.
1 = Enables the setting of the RI_STS to generate a wake event.
Reserved.
TCOSCI_EN—R/W.
0 = Disable.
1 = Enables the setting of the TCOSCI_STS to generate an SCI.
AC97_EN—R/W.
0 = Disable.
1 = Enables the setting of the AC97_STS to generate a wake event.
USB2_EN—R/W.
0 = Disable.
1 = Enables the setting of the USB2_STS to generate a wake event.
USB1_EN—R/W.
0 = Disable.
1 = Enables the setting of the USB1_STS to generate a wake event.
THRM#_POL—R/W. This bit controls the polarity of the THRM# pin needed to set the
THRM_STS bit.
0 = Low value on the THRM# signal will set the THRM_STS bit.
1 = HIGH value on the THRM# signal will set the THRM_STS bit.
Reserved.
THRM_EN—R/W.
0 = Disable.
1 = Active assertion of the THRM# signal (as defined by the THRM_POL bit) will set the
THRM_STS bit and generate a power management event (SCI or SMI).
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Intel^® 82801CA ICH3-S Datasheet