82801CA Datasheet, PDF (221/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.18.1.17 Input Slot 3: PCM Record Left Channel
Input slot 3 is the left channel input of the codec. The ICH3 supports 16-bit sample resolution.
Samples transmitted to the ICH3 must be in left/right channel order.
5.18.1.18 Input Slot 4: PCM Record Right Channel
Input slot 4 is the right channel input of the codec. The ICH3 supports 16-bit sample resolution.
Samples transmitted to the ICH3 must be in left/right channel order.
5.18.1.19 Input Slot 5: Modem Line
Input slot 5 contains MSB justified modem data. The ICH3 supports 16-bit sample resolution.
5.18.1.20 Input Slot 6: Optional Dedicated Microphone Record Data
Input slot 6 is a third PCM system input channel available for dedicated use by a microphone. This
input channel supplements a true stereo output which enables more precise echo cancellation
algorithm for speakerphone applications. The ICH3 supports 16-bit resolution for slot 6 input.
5.18.1.21 Input Slots 7–11: Reserved
Input frame slots 7–11 are reserved for future use and should be stuffed with zeros by the codec,
per the Audio Codec ’97, Revision 2.2 specification.
5.18.1.22 Input Slot 12: I/O status
The status of the GPIOs configured as inputs are to be returned on this slot in every frame. The data
returned on the latest frame is accessible to software by reading the register at offset 54h/D4h in the
codec I/O space. Only the 16 MSBs are used to return GPI status. Bit 0 of this slot indicates the
GPI status. Whenever a GPI changes state, this bit gets set for one frame by the codec. This bit can
cause an interrupt to the processor if enabled via the global control register.
Reads from 54h/D4h will not be transmitted across the link in slot 1 and 2. The data from the most
recent slot 12 is returned on reads from offset 54h/D4h.
Intel^® 82801CA ICH3-S Datasheet
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