82801CA Datasheet, PDF (428/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

AC ’97 Audio Controller Registers (D31:F5)
13.2.9
GLOB_STA—Global Status Register
I/O Address:
Default Value:
Lockable:
NABMBAR + 30h
00300000h
No
Attribute:
Size:
Power Well:
RO, R/W, R/WC
32 bits
Core
Bit
Description
31:22
21
20
19:18
17
16
15
14
13
12
11
10
9
8
7
Reserved.
6 Channel Capability (6CH_CAP)—RO. Hardwired to 1 in the ICH3.
0 = The AC ’97 Controller does not support 6-channel PCM Audio output.
1 = The AC ’97 Controller supports 6-channel PCM Audio output.
4 Channel Capability (4CH_CAP)—RO. Hardwired to ‘1’ in the ICH3.
0 = The AC ’97 Controller does not support 4-channel PCM Audio output.
1 = The AC ’97 Controller supports 4-channel PCM Audio output.
Reserved.
MD3—R/W. Power down semaphore for Modem. This bit exists in the suspend well and maintains
context across power states (except G3). The bit has no hardware function. It is used by software in
conjunction with the AD3 bit to coordinate the entry of the two codecs into D3 state.
AD3—R/W. Power down semaphore for Audio. This bit exists in the suspend well and maintains
context across power states (except G3). The bit has no hardware function. It is used by software in
conjunction with the MD3 bit to coordinate the entry of the two codecs into D3 state.
Read Completion Status (RCS)—R/WC. This bit indicates the status of codec read completions.
0 = A codec read completes normally.
1 = A codec read results in a time-out. The bit remains set until being cleared by software writing a
1 to the bit location.
Bit 3 of slot 12—RO. Display bit 3 of the most recent slot 12.
Bit 2 of slot 12—RO. Display bit 2 of the most recent slot 12.
Bit 1 of slot 12—RO. Display bit 1 of the most recent slot 12.
Secondary Resume Interrupt (SRI)—R/WC. This bit indicates that a resume event occurred on
AC_SDIN[1].
0 = Cleared by writing a 1 to this bit position.
1 = Resume event occurred.
Primary Resume Interrupt (PRI)—R/WC. This bit indicates that a resume event occurred on
AC_SDIN[0].
0 = Cleared by writing a 1 to this bit position.
1 = Resume event occurred.
Secondary Codec Ready (SCR)—RO. Reflects the state of the codec ready bit in AC_SDIN[1].
Bus masters ignore the condition of the codec ready bits, so software must check this bit before
starting the bus masters. Once the codec is “ready”, it must never go “not ready” spontaneously.
0 = Not Ready.
1 = Ready.
Primary Codec Ready (PCR)—RO. Reflects the state of the codec ready bit in AC_SDIN [0]. Bus
masters ignore the condition of the codec ready bits, so software must check this bit before starting
the bus masters. Once the codec is “ready”, it must never go “not ready” spontaneously.
0 = Not Ready.
1 = Ready.
Mic In Interrupt (MINT)—RO. This bit indicates that one of the Mic in channel interrupts occurred.
0 = When the specific interrupt is cleared, this bit will be cleared.
1 = Interrupt occurred.
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Intel^® 82801CA ICH3-S Datasheet