82801CA Datasheet, PDF (206/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.17.5 SMBALERT#
SMBALERT# is multiplexed with GPIO[11]. When enable and the signal is asserted, The ICH3
can generate an interrupt, an SMI# or a wake event from S1–S4.
Note: Any event on SMBALERT# (regardless whether it is programmed as a GPIO or not), causes the
event message to be sent in “heartbeat mode.”
5.17.6
SMBus Slave Interface
The ICH3’s SMBus Slave interface is accessed via the SMLINK[1:0] signals. The SMBus slave
logic will not generate or handle receiving the PEC byte and will only act as a Legacy Alerting
Protocol (Alert on LAN) device. The slave interface allows the ICH3 to decode cycles, and allows
an external microcontroller to perform specific actions. Key features and capabilities include:
• Supports decode of three types of messages: Byte Write, Byte Read, and Host Notify
• Receive Slave Address Register: This is the address that the ICH3 decodes. A default value is
provided so that the slave interface can be used without the processor having to program this
register.
• Receive Slave Data Register in the SMBus I/O space that includes the data written by the
external microcontroller
• Registers that the external microcontroller can read to get the state of the ICH3. See Table 5-95
• Status bits to indicate that the SMLink/SMBus slave logic caused an interrupt or SMI# due to
the reception of a message that matched the slave address.
— Bit 0 of the Slave Status Register for the Host Notify command
— Bit 16 of the SMI Status Register (Section 9.8.3.12) for all others
If a master leaves the clock and data bits of the SMLink interface at '1' for 50 µs or more in the
middle of a cycle, the ICH3 slave logic's behavior is undefined. This is interpreted as an
unexpected idle and should be avoided when performing management activities to the slave logic.
When an external microcontroller accesses the SMBus Slave Interface over the SMLink, a
translation in the address is needed to accommodate the least significant bit used for read/write
control. For example, if the ICH3 slave address (RCV_SLVA) is left at 44h (default), the external
microcontroller would use an address of 88h/89h (write/read).
206
Intel^® 82801CA ICH3-S Datasheet