82801CA Datasheet, PDF (5/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Contents
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Introduction ........................................................................................................... 29
1.1 About This Datasheet ....................................................................................29
1.2 Overview ........................................................................................................31
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Signal Description ..............................................................................................37
2.1 Hub Interface to Host Controller ....................................................................39
2.2 Link to LAN Connect ......................................................................................39
2.3 EEPROM Interface ........................................................................................39
2.4 Firmware Hub Interface .................................................................................40
2.5 PCI Interface ..................................................................................................40
2.6 IDE Interface ..................................................................................................43
2.7 LPC Interface .................................................................................................44
2.8 Interrupt Interface...........................................................................................44
2.9 USB Interface.................................................................................................45
2.10 Power Management Interface........................................................................45
2.11 Processor Interface........................................................................................46
2.12 SMBus Interface ............................................................................................48
2.13 System Management Interface ......................................................................48
2.14 Real Time Clock Interface..............................................................................48
2.15 Other Clocks ..................................................................................................49
2.16 Miscellaneous Signals ...................................................................................49
2.17 AC ’97 Link.....................................................................................................49
2.18 General Purpose I/O ......................................................................................50
2.19 Power and Ground.........................................................................................51
2.20 Pin Straps ......................................................................................................52
2.20.1 Functional Straps ..............................................................................52
2.20.2 External RTC Circuitry ......................................................................53
2.20.3 V5REF / Vcc3_3 Sequencing Requirements ....................................53
2.20.4 Test Signals ......................................................................................54
2.20.4.1 Test Mode Selection..........................................................54
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Power Planes and Pin States .........................................................................55
3.1 Power Planes.................................................................................................55
3.2 Integrated Pull-Ups and Pull-Downs ..............................................................56
3.3 IDE Integrated Series Termination Resistors.................................................56
3.4 Output and I/O Signals Planes and States ....................................................57
3.5 Power Planes for Input Signals......................................................................60
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Intel^® ICH3 and System Clock Domains....................................................63
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Functional Description .....................................................................................65
5.1 Hub Interface to PCI Bridge (D30:F0)............................................................65
5.1.1 PCI Bus Interface..............................................................................65
5.1.2 PCI-to-PCI Bridge Model ..................................................................66
5.1.3 IDSEL to Device Number Mapping ...................................................66
5.1.4 SERR# Functionality.........................................................................66
5.1.5 Parity Error Detection........................................................................68
5.1.6 Standard PCI Bus Configuration Mechanism ...................................69
Intel^® 82801CA ICH3-S Datasheet
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