82801CA Datasheet, PDF (403/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

SMBus Controller Registers (D31:F3)
12.1.13
HOSTC—Host Configuration Register (SMBUS—D31:F3)
Address Offset: 40h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:3 Reserved.
I²C_EN—R/W.
2
0 = SMBus behavior.
1 = The ICH3 is enabled to communicate with I²C devices. This will change the formatting of some
commands.
SMB_SMI_EN—R/W.
0 = SMBus interrupts will not generate an SMI#.
1 1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. Refer to
Section 5.17.4, “Interrupts / SMI#” on page 5-205.
This bit needs to be set for SMBALERT# to be enabled.
SMBus Host Enable (HST_EN)—R/W.
0 = Disable the SMBus Host Controller.
0 _{1 = Enable. The SMB Host Controller interface is enabled to execute commands. The INTREN bit}
needs to be enabled for the SMB Host Controller to interrupt or SMI#. Note that the SMB Host
Controller will not respond to any new requests until all interrupt requests have been cleared.
Intel^® 82801CA ICH3-S Datasheet
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