82801CA Datasheet, PDF (189/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
OUT Transaction
A function may respond to an OUT transaction with a STALL, ACK, or NAK. If the transaction
contained corrupted data, it will issue no response.
SETUP Transaction
Setup defines a special type of host to function data transaction which permits the host to initialize
an endpoint’s synchronization bits to those of the host. Upon receiving a Setup transaction, a
function must accept the data. Setup transactions cannot be STALLed or NAKed and the receiving
function must accept the Setup transfer’s data. If a non-control endpoint receives a SETUP PID, it
must ignore the transaction and return no response.
5.16.6
5.16.6.1
USB Interrupts
There are two general groups of USB interrupt sources, those resulting from execution of
transactions in the schedule, and those resulting from an ICH3 operation error. All transaction-
based sources can be masked by software through the ICH3’s Interrupt Enable Register.
Additionally, individual transfer descriptors can be marked to generate an interrupt on completion.
When the ICH3 drives an interrupt for USB, it internally drives the PIRQ[A]# pin for USB
function #0, PIRQ[D]# pin for USB function #1, and the PIRQ[C]# pin for USB function #2, until
all sources of the interrupt are cleared. In order to accommodate some operating systems, the
Interrupt Pin Register must contain a different value for each function of this new multi-function
device.
Transaction Based Interrupts
These interrupts are not signaled until after the status for the last complete transaction in the frame
has been written back to host memory. This guarantees that software can safely process through
(Frame List Current Index -1) when it is servicing an interrupt.
CRC Error / Time-Out
A CRC/Time-out error occurs when a packet transmitted from the ICH3 to a USB device or a
packet transmitted from a USB device to the ICH3 generates a CRC error. The ICH3 is informed of
this event by a time-out from the USB device or by the ICH3’s CRC checker generating an error on
reception of the packet. Additionally, a USB bus time-out occurs when USB devices do not
respond to a transaction phase within 19 bit times of an EOP. Either of these conditions will cause
the C_ERR field of the TD to decrement.
When the C_ERR field decrements to zero, the following occurs:
• The active bit in the TD is cleared
• The stalled bit in the TD is set
• The CRC/Time-out bit in the TD is set.
• At the end of the frame, the USB error interrupt bit is set in the HC status register.
If the CRC/Time-out interrupt is enabled in the Interrupt Enable Register, a hardware interrupt will
be signaled to the system.
Intel^® 82801CA ICH3-S Datasheet
189