82801CA Datasheet, PDF (348/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
Bit
Description
PM1_STS_REG—RO. This is an ORs of the bits in the ACPI PM1 Status Register (offset
PMBASE+00h) that can cause an SMI#.
8
0 = SMI# was not generated by a PM1_STS event.
1 = SMI# was generated by a PM1_STS event.
7 Reserved.
SWSMI_TMR_STS—R/WC.
6 ^{1 = Set by the hardware when the Software SMI# Timer expires.}
0 = Software clears this bit by writing a 1 to the bit location.
APM_STS—R/WC.
5 _{0 = Software clears this bit by writing a 1 to the bit location.}
1 = SMI# was generated by a write access to the APM control register with the APMC_EN bit set.
SLP_SMI_STS—R/WC.
4 ^{1 = Indicates an SMI# was caused by a write of 1 to SLP_EN bit when SLP_SMI_EN bit is also set.}
0 = Software clears this bit by writing a 1 to the bit location.
LEGACY_USB_STS—RO. This bit is a logical OR of each of the SMI status bits in the USB Legacy
Keyboard/Mouse Control Registers ANDed with the corresponding enable bits. This bit will not be
3 ^{active if the enable bits are not set.}
0 = SMI# was not generated by USB Legacy event.
1 = SMI# was generated by USB Legacy event.
BIOS_STS—R/WC.
2 ^{0 = This bit cleared by software writing a 1 to its bit position.}
1 = SMI# was generated due to ACPI software requesting attention (writing a 1 to the GBL_RLS bit
with the BIOS_EN bit set).
1:0 Reserved.
9.8.3.13
MON_SMI—Device Monitor SMI Status and Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE +40h
0000h
No
Core
Attribute:
Size:
Usage:
R/W, R/WC
16-bit
Legacy Only
Bit
Description
DEV[7:4]_TRAP_STS—R/WC. Bit 12 corresponds to Monitor 4, bit 13 corresponds to Monitor 5 etc.
15:12 _{0 = SMI# was not caused by the associated device monitor.}
1 = SMI# was caused by an access to the corresponding device monitor’s I/O range.
DEV[7:4]_TRAP_EN—R/W. Bit 8 corresponds to Monitor 4, bit 9 corresponds to Monitor 5 etc.
11:8 _{0 = Disable.}
1 = Enables SMI# due to an access to the corresponding device monitor’s I/O range.
7:0 Reserved.
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Intel^® 82801CA ICH3-S Datasheet