82801CA Datasheet, PDF (26/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

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ACPI and Legacy I/O Register Map............................................................. 336
TCO I/O Register Map ................................................................................. 352
Summary of GPIO Implementation.............................................................. 358
Registers to Control GPIO ........................................................................... 360
PCI Configuration Map (IDE-D31:F1) .......................................................... 365
Bus Master IDE I/O Registers...................................................................... 377
PCI Configuration Map (USB—D29:F0/F1/F2) ............................................ 381
USB I/O Registers ....................................................................................... 389
Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop
(Bit 0) Operation .......................................................................................... 391
PCI Configuration Registers (SMBUS—D31:F3)......................................... 399
SMB I/O Registers ....................................................................................... 404
PCI Configuration Map (Audio—D31:F5) .................................................... 413
Intel^® ICH3 Audio Mixer Register Configuration .......................................... 420
Native Audio Bus Master Control Registers ................................................ 422
PCI Configuration Map (Modem—D31:F6).................................................. 431
Intel^® ICH3 Modem Mixer Register Configuration ....................................... 437
Modem Registers......................................................................................... 438
Intel^® ICH3-S Ball List by Signal Name ....................................................... 450
Intel^® ICH3-S Power Consumption Estimates ............................................. 458
DC Characteristics Input Signal Association ............................................... 459
DC Input Characteristics.............................................................................. 460
DC Characteristic Output Signal Association .............................................. 461
DC Output Characteristics ........................................................................... 462
Other DC Characteristics ............................................................................. 463
Clock Timings .............................................................................................. 464
PCI Interface Timing .................................................................................... 465
IDE PIO and Multiword DMA ModeTiming .................................................. 466
Ultra ATA Timing (Mode 0, Mode 1, Mode 2) .............................................. 467
Ultra ATA Timing (Mode 3, Mode 4, Mode 5) .............................................. 469
Universal Serial Bus Timing......................................................................... 471
IOAPIC Bus Timing...................................................................................... 472
SMBus Timing ............................................................................................. 472
AC ’97 Timing .............................................................................................. 472
LPC Timing .................................................................................................. 472
Miscellaneous Timings ................................................................................ 473
Power Sequencing and Reset Signal Timings............................................. 473
Power Management Timings ....................................................................... 474
Test Mode Selection .................................................................................... 487
XOR Test Pattern Example ......................................................................... 488
XOR Chain #1 (RTCRST# Asserted for 4 PCI Clocks While
PWROK Active) ........................................................................................... 489
XOR Chain #2 (RTCRST# Asserted for 5 PCI Clocks While
PWROK Active) ........................................................................................... 490
XOR Chain #3 (RTCRST# asserted for 6 PCI Clocks While
PWROK Active) ........................................................................................... 491
XOR Chain #4 (RTCRST# Asserted for 7 PCI Clocks While
PWROK Active) ........................................................................................... 492
Signals Not in XOR Chain ........................................................................... 493
Intel^® ICH3 PCI Configuration Registers ..................................................... 495
Intel^® ICH3 Fixed I/O Registers ................................................................... 503
Intel^® ICH3 Variable I/O Registers............................................................... 508
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Intel^® 82801CA ICH3-S Datasheet