82801CA Datasheet, PDF (367/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

IDE Controller Registers (D31:F1)
10.1.4
10.1.5
STS—Device Status Register (IDE—D31:F1)
Address Offset: 06–07h
Default Value: 0280h
Attribute:
Size:
R/WC, RO
16 bits
Bit
Description
15 Detected Parity Error (DPE)—RO. Hardwired to 0.
14 Signaled System Error (SSE)—RO. Hardwired to 0.
Received Master Abort (RMA)—R/WC.
13 _{0 = Cleared by writing a 1 to it.}
1 = Bus Master IDE interface function, as a master, generated a master-abort.
12 Reserved as 0—RO.
Signaled Target Abort (STA)—R/WC.
11 ^{0 = Cleared by writing a 1 to it.}
1 = ICH3 IDE interface function is targeted with a transaction that the ICH3 terminates with a target
abort.
DEVSEL# Timing Status (DEV_STS)—RO.
10:9 _{01 = Hardwired; however, the ICH3 does not have a real DEVSEL# signal associated with the IDE}
unit, so these bits have no effect.
8 Data Parity Error Detected (DPED)—RO. Hardwired to 0.
7 Fast Back to Back (FB2B)—RO. Hardwired to 1.
6 User Definable Features (UDF)—RO. Hardwired to 0.
5 66 MHz Capable (66MHZ_CAP)—RO. Hardwired to 0.
4:0 Reserved.
RID—Revision Identification Register (IDE—D31:F1)
Address Offset: 08h
Default Value: See Note
Attribute:
Size:
RO
8 Bits
Bit
Description
7:0
Revision Identification Value—RO.
NOTE: Refer to the Specification Update for the Revision ID.
Intel^® 82801CA ICH3-S Datasheet
367