82801CA Datasheet, PDF (89/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.3.1.7
SYNC Error Indication
The SYNC protocol allows the peripheral to report an error via the LAD[3:0] = 1010b encoding.
The intent of this encoding is to give peripherals a method of communicating errors to aid higher
layers with more robust error recovery.
If the ICH3 was reading data from a peripheral, data will still be transferred in the next two nibbles.
This data may be invalid, but it must be transferred by the peripheral. If the ICH3 was writing data
to the peripheral, the data had already been transferred.
In the case of multiple byte cycles, such as for memory and DMA cycles, an error SYNC
terminates the cycle. Therefore, if the ICH3 is transferring 4 bytes from a device, if the device
returns the error SYNC in the first byte, the other three bytes will not be transferred.
Upon recognizing the SYNC field indicating an error, the ICH3 will treat this the same as IOCHK#
going active on the ISA bus.
5.3.1.8 LFRAME# Usage
Start of Cycle
For Memory, I/O, and DMA cycles, the ICH3 asserts LFRAME# for 1 clock at the beginning of the
cycle (Figure 5-7). During that clock, the ICH3 drives LAD[3:0] with the proper START field.
Figure 5-7. Typical Timing for LFRAME#
LCLK
LFRAME#
LAD[3:0]
Start
ADDR TAR Sync Data
1 CYCTYPE 1 - 8
2
1-n
2
Clock Dir & Size Clocks Clocks Clocks Clocks
TAR
2
Clocks
Start
1
Clock
Intel^® 82801CA ICH3-S Datasheet
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