82801CA Datasheet, PDF (377/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

IDE Controller Registers (D31:F1)
Bit
Description
Primary Drive 1 Base Clock (PCB1)—R/W.
1
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings.
Primary Drive 0 Base Clock (PCB0)—R/W.
0
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings.
10.2 Bus Master IDE I/O Registers (D31:F1)
The bus master IDE function uses 16 bytes of I/O space, allocated via the BMIBA register, located
in Device 31:Function 1 Configuration space, offset 20h. All bus master IDE I/O space registers
can be accessed as byte, word, or dword quantities. Reading reserved bits returns an indeterminate,
inconsistent value, and writes to reserved bits have no affect (but should not be attempted). The
description of the I/O registers is shown below in Table 10-2.
Table 10-2. Bus Master IDE I/O Registers
Offset
00h
01h
02h
03h
04–07h
08h
09h
0Ah
0Bh
0C–0Fh
Mnemonic
BMICP
—
BMISP
—
BMIDP
BMICS
—
BMISS
—
BMIDS
Register
Command Register Primary
Reserved
Status Register Primary
Reserved
Descriptor Table Pointer Primary
Command Register Secondary
Reserved
Status Register Secondary
Reserved
Descriptor Table Pointer Secondary
Default
00h
00h
00h
00h
xxxxxxxxh
00h
00h
00h
00h
xxxxxxxxh
Type
R/W
RO
R/WC
RO
R/W
R/W
RO
R/WC
RO
R/W
Intel^® 82801CA ICH3-S Datasheet
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