82801CA Datasheet, PDF (86/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.3.1.1 LPC Cycle Types
The ICH3 implements all of the cycle types described in the Low Pin Count (LPC) Interface
Specification, Revision 1.0. Table 5-2 shows the cycle types supported by the ICH3.
Table 5-2. LPC Cycle Types Supported
Cycle Type
Memory Read
Memory Write
I/O Read
I/O Write
DMA Read
DMA Write
Bus Master Read
Bus Master Write
Comment
Single: 1 byte only
Single: 1 byte only
1 byte only. ICH3 breaks up 16- and 32-bit processor cycles into multiple 8-bit
transfers. See Note 1 below.
1 byte only. ICH3 breaks up 16- and 32-bit processor cycles into multiple 8-bit
transfers. See Note 1 below.
Can be 1, or 2 bytes
Can be 1, or 2 bytes
Can be 1, 2, or 4 bytes. (See Note 2 below)
Can be 1, 2, or 4 bytes. (See Note 2 below)
NOTES:
1. For memory cycles below 16 MB which do not target enabled FWH ranges, the ICH3 will perform standard
LPC memory cycles. It will only attempt 8-bit transfers. If the cycle appears on PCI as a 16-bit transfer, it will
appear as two consecutive 8-bit transfers on LPC. Likewise, if the cycle appears as a 32-bit transfer on PCI,
it will appear as four consecutive 8-bit transfers on LPC. If the cycle is not claimed by any peripheral, it will be
subsequently aborted, and the ICH3 will return a value of all 1s to the processor. This is done to maintain
compatibility with ISA memory cycles where pull-up resistors would keep the bus high if no device responds.
2. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer can be to any
address. However, the 2-byte transfer must be word aligned (i.e., with an address where A0=0). A dword
transfer must be dword aligned (i.e., with an address where A1and A0 are both 0)
5.3.1.2 Start Field Definition
Table 5-3. Start Field Bit Definitions
Bits[3:0]
Encoding
0000
0010
0011
1111
Start of cycle for a generic target.
Grant for bus master 0.
Grant for bus master 1.
Stop/Abort: End of a cycle for a target.
Definition
NOTE: All other encodings are Reserved.
86
Intel^® 82801CA ICH3-S Datasheet