82801CA Datasheet, PDF (265/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.13
8.1.14
8.1.15
SMLT—Secondary Master Latency Timer Register
(HUB-PCI—D30:F0)
Offset Address: 1Bh
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This Master Latency Timer (MLT) controls the amount of time that the ICH3 will continue to burst
data as a master on the PCI bus. When the ICH3 starts the cycle after being granted the bus, the
counter is loaded and starts counting down from the assertion of FRAME#. If the internal grant to
this device is removed, then the expiration of the MLT counter will result in the de-assertion of
FRAME#. If the internal grant has not been removed, then the ICH3 can continue to own the bus.
Bit
Description
7:3
Master Latency Timer Count (MLTC)—R/W. 5-bit value that indicates the number of PCI clocks, in
8-clock increments, that the ICH3 will remain as master of the bus.
2:0 Reserved.
IOBASE—I/O Base Register (HUB-PCI—D30:F0)
Offset Address: 1Ch
Default Value: F0h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:4
I/O Address Base Bits [15:12]—R/W. I/O Base bits corresponding to address lines 15:12 for 4-KB
alignment. Bits 11:0 are assumed to be padded to 000h.
I/O Addressing Capability—RO. This is hardwired to 0h, indicating that the hub interface to PCI
3:0 bridge does not support 32-bit I/O addressing. This means that the I/O Base & Limit Upper Address
registers must be read only.
IOLIM—I/O Limit Register (HUB-PCI—D30:F0)
Offset Address: 1Dh
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:4
I/O Address Limit Bits [15:12]—R/W. I/O Base bits corresponding to address lines 15:12 for 4-KB
alignment. Bits 11:0 are assumed to be padded to FFFh.
I/O Addressing Capability—RO. This is hardwired to 0h, indicating that the hub interface-to-PCI
3:0 bridge does not support 32-bit I/O addressing. This means that the I/O Base & Limit Upper Address
registers must be read only.
Intel^® 82801CA ICH3-S Datasheet
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