82801CA Datasheet, PDF (343/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
Bit
Description
RI_STS—R/WC.
8
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when the RI# input signal goes active.
SMBus Wake Status (SMB_WAK_STS)—R/WC. The SMBus controller can independently
cause an SMI# or SCI, so this bit does not need to do so (unlike the other bits in this register).
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware to indicate that the wake event was caused by the ICH3’s SMBus logic.This
7
bit will be set by the WAKE/SMI# command type, even if the system is already awake. The
SMI handler should then clear this bit.
NOTE: This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the system is
in the S0 state. Therefore, to avoid an instant wake on subsequent transitions to sleep
states, software must clear this bit after each reception of the Wake/SMI# command or
just prior to entering the sleep state.
TCOSCI_STS—R/WC.
6
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when the TCO logic causes an SCI.
AC97_STS—R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
5
1 = Set by hardware when the codecs are attempting to wake the system. The AC97_STS bit
gets set only from the following two cases:
1. ACSDIN[1] or ACSDIN[0] is high and BITCLK is not oscillating, or
2. The GSCI bit is set (section 13.2.9, NAMBAR +30h, bit 0).
USB2_STS—R/WC.
4
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when USB Controller 2 needs to cause a wake. Wake event will be
generated if the corresponding USB2_EN bit is set.
USB1_STS—R/WC.
3
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when USB Controller 1 needs to cause a wake. Wake event will be
generated if the corresponding USB1_EN bit is set.
2
Reserved.
Thermal Interrupt Override Status (THRMOR_STS)—R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1
1 = This bit is set by hardware anytime a thermal over-ride condition occurs and starts throttling
the processor’s clock at the THRM_DTY ratio. This will not cause an SMI#, SCI, or wake
event.
Thermal Interrupt Status (THRM_STS)—R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
0
1 = Set by hardware anytime the THRM# signal is driven active as defined by the THRM_POL
bit. Additionally, if the THRM_EN bit is set, then the setting of the THRM_STS bit will also
generate a power management event (SCI or SMI#).
Intel^® 82801CA ICH3-S Datasheet
343