82801CA Datasheet, PDF (70/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.1.7
PCI Dual Address Cycle (DAC) Support
The ICH3 supports Dual Address Cycle (DAC) format on PCI for cycles from PCI initiators to
main memory. This allows PCI masters to generate an address up to 44 bits. The size of the actual
supported memory space will be determined by the memory controller and the processor.
The DAC mode is only supported for PCI adapters and is not supported for any of the internal PCI
masters (IDE, LAN, USB 1.1, AC’97, 8237 DMA, etc.).
When a PCI master wants to initiate a cycle with an address above 4 GB, it uses the following
behavioral rules (See PCI 2.2 Specification, Section 3.9 for more details):
1. On the first clock of the cycle (when FRAME# is first active), the peripheral uses the DAC
encoding on the C/BE# signals. This unique encoding is 1101.
2. Also during the first clock, the peripheral drives the AD[31:0] signals with the low address.
3. On the second clock, the peripheral drives AD[31:0] with the high address. The address is
right justified: A[43:32] appear on AD[12:0]. The value of AD[31:13] is expected to be 0;
however, the ICH3 ignores these bits. The C/BE# signals indicate the bus command type
(Memory Read, Memory Write, etc.)
4. The rest of the cycle proceeds normally.
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Intel^® 82801CA ICH3-S Datasheet