82801CA Datasheet, PDF (113/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.8
5.8.1
Advanced Interrupt Controller (APIC) (D31:F0)
In addition to the standard ISA compatible interrupt controller (PIC) described in the previous
chapter, the ICH3 incorporates the Advanced Programmable Interrupt Controller (APIC). While
the standard interrupt controller is intended for use in a uni-processor system, APIC can be used in
either a uni-processor or multi-processor system.
Interrupt Handling
The I/O APIC handles interrupts very differently than the 8259. Briefly, these differences are:
• Method of Interrupt Transmission. The I/O APIC transmits interrupts through a three wire
bus, and interrupts are handled without the need for the processor to run an interrupt
acknowledge cycle.
• Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the interrupt
number. For example, interrupt 10 can be given a higher priority than interrupt 3.
• More Interrupts. The I/O APIC in the ICH3 supports a total of 24 interrupts.
• Multiple Interrupt Controllers. The I/O APIC interrupt transmission protocol has an
arbitration phase, which allows for multiple I/O APICs in the system with their own interrupt
vectors. The ICH3 I/O APIC must arbitrate for the APIC bus before transmitting its interrupt
message.
Intel^® 82801CA ICH3-S Datasheet
113