82801CA Datasheet, PDF (295/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.1.32
9.1.33
GEN2_DEC—LPC I/F Generic Decode Range 2 Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
ECh–EDh
00h
Yes
Attribute:
Size:
Power Well:
R/W
16-bit
Core
Bit
Description
Generic I/O Decode Range 2 Base Address (GEN2_BASE)—R/W. This address is aligned on a
64-byte boundary, and must have address lines 31:16 as 0.
15:4
Note that this generic decode is for I/O addresses only, not memory addresses. The size of this
range is 16 bytes.
3:1 Reserved. Read as 0.
Generic I/O Decode Range 2 Enable (GEN2_EN)—R/W.
0 _{0 = Disable.}
1 = Accesses to the GEN2 I/O range will be forwarded to the LPC I/F.
FWH_SEL2—FWH Select 2 Register (LPC I/F—D31:F0)
Offset Address: EEh–EFh
Default Value: 4567h
Attribute:
Size:
R/W
32 bits
Bit
Description
15:12
11:8
7:4
3:0
FWH_70_IDSEL—R/W. IDSEL for two 1M FWH memory ranges.
The IDSEL programmed in this field addresses the following memory ranges:
FF70 0000h—FF7F FFFFh
FF30 0000h—FF3F FFFFh
FWH_60_IDSEL—R/W. IDSEL for two 1M FWH memory ranges.
The IDSEL programmed in this field addresses the following memory ranges:
FF60 0000h—FF6F FFFFh
FF20 0000h—FF2F FFFFh
FWH_50_IDSEL—R/W. IDSEL for two 1M FWH memory ranges.
The IDSEL programmed in this field addresses the following memory ranges:
FF50 0000h—FF5F FFFFh
FF10 0000h—FF1F FFFFh
FWH_40_IDSEL—R/W. IDSEL for two 1M FWH memory ranges.
The IDSEL programmed in this field addresses the following memory ranges:
FF40 0000h—FF4F FFFFh
FF00 0000h—FF0F FFFFh
Intel^® 82801CA ICH3-S Datasheet
295