82801CA Datasheet, PDF (375/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

IDE Controller Registers (D31:F1)
10.1.23
SDMA_TIM—Synchronous DMA Timing Register
(IDE—D31:F1)
Address Offset: 4A–4Bh
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Bit
Description
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
Reserved.
Secondary Drive 1 Cycle Time (SCT1)—R/W. For Ultra ATA mode. The setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
SCB1 = 0 (33 MHz clk)
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks
10 = CT 2 clocks, RP 4 clocks
11 = Reserved
SCB1 = 1 (66 MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8 clocks
10 = CT 2 clocks, RP 8 clocks
11 = Reserved
FAST_SCB1 = 1 (133 MHz clk)
00 = Reserved
01 = CT 3 clks, RP 16 clks
10 = Reserved
11 = Reserved
Reserved.
Secondary Drive 0 Cycle Time (SCT0)—R/W. For Ultra ATA mode. The setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
SCB1 = 0 (33 MHz clk)
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks
10 = CT 2 clocks, RP 4 clocks
11 = Reserved
SCB1 = 1 (66 MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8 clocks
10 = CT 2 clocks, RP 8 clocks
11 = Reserved
FAST_SCB1 = 1 (133 MHz clk)
00 = Reserved
01 = CT 3 clks, RP 16 clks
10 = Reserved
11 = Reserved
Reserved.
Primary Drive 1 Cycle Time (PCT1)—R/W. For Ultra ATA mode, the setting of these bits
determines the minimum write strobe cycle time(CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
PCB1 = 0 (33 MHz clk)
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks
10 = CT 2 clocks, RP 4 clocks
11 = Reserved
PCB1 = 1 (66 MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8 clocks
10 = CT 2 clocks, RP 8 clocks
11 = Reserved
FAST_PCB1 = 1 (133 MHz clk)
00 = Reserved
01 = CT 3 clks, RP 16 clks
10 = Reserved
11 = Reserved
Reserved.
Primary Drive 0 Cycle Time (PCT0)—R/W. For Ultra ATA mode, the setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
PCB1 = 0 (33 MHz clk)
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks
10 = CT 2 clocks, RP 4 clocks
11 = Reserved
PCB1 = 1 (66 MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8 clocks
10 = CT 2 clocks, RP 8 clocks
11 = Reserved
FAST_PCB1 = 1 (133 MHz clk)
00 = Reserved
01 = CT 3 clks, RP 16 clks
10 = Reserved
11 = Reserved
Intel^® 82801CA ICH3-S Datasheet
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