82801CA Datasheet, PDF (341/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.8.3.5
PROC_CNT—Processor Control Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 10h
(ACPI P_BLK)
00000000h
No (bits 7:5 are write once)
Core
Attribute:
Size:
Usage:
R/W
32-bit
ACPI or Legacy
Bit
Description
31:18
17
16:9
8
7:5
4
3:1
0
Reserved.
Throttle Status (THTL_STS)—RO.
0 = No clock throttling is occurring (maximum processor performance).
1 = Indicates that the clock state machine is in some type of low power state (where the processor
is not running at its maximum performance): thermal throttling or hardware throttling.
Reserved.
Force Thermal Throttling (FORCE_THTL)—R/W. Software can set this bit to force the thermal
throttling function. This has the same effect as the THRM# signal being active for 2 seconds.
0 = No forced throttling.
1 = Throttling at the duty cycle specified in THRM_DTY starts immediately (no 2 second delay), and
no SMI# is generated.
THRM_DTY. This write-once 3-bit field determines the duty cycle of the throttling when the thermal
override condition occurs. The duty cycle indicates the approximate percentage of time the
STPCLK# signal is asserted while in the throttle mode. The STPCLK# throttle period is 1024
PCICLKs. Note that the throttling only occurs if the system is in the C0 state. If in the C2 state, no
throttling occurs.
There is no enable bit for thermal throttling, because it should not be disabled. Once the
THRM_DTY field is written, any subsequent writes will have no effect until PCIRST# goes active.
THRM_DTY
000
001
010
011
100
101
110
111
Throttle Mode
RESERVED (Default)
(Will be 50%)
87.5%
75.0%
62.5%
50%
37.5%
25%
12.5%
PCI Clocks
512
896
768
640
512
384
256
128
THTL_EN. When set and the system is in a C0 state, it enables a processor-controlled STPCLK#
throttling. The duty cycle is selected in the THTL_DTY field.
0 = Disable.
1 = Enable.
THTL_DTY. This 3-bit field determines the duty cycle of the throttling when the THTL_EN bit is set.
The duty cycle indicates the approximate percentage of time the STPCLK# signal is asserted (low)
while in the throttle mode. The STPCLK# throttle period is 1024 PCICLKs.
THTL_DTY
000
001
010
011
100
101
110
111
Throttle Mode
RESERVED (Default)
(Will be 50%)
87.5%
75.0%
62.5%
50%
37.5%
25%
12.5%
PCI Clocks
512
896
768
640
512
384
256
128
Reserved.
Intel^® 82801CA ICH3-S Datasheet
341