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82801CA Datasheet, PDF (293/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S) | |||
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LPC I/F Bridge Registers (D31:F0)
Bit
Description
ADLIB_LPC_ENâR/W.
7 0 = Disable.
1 = Enables the decoding of the I/O locations 388hâ38Bh to the LPC interface.
MSS_LPC_ENâR/W.
6
0 = Disable.
1 = Enables the decoding of the MSS range to the LPC interface. This range is selected in the
LPC_Sound Decode Range Register.
MIDI_LPC_ENâR/W.
5
0 = Disable.
1 = Enables the decoding of the MIDI range to the LPC interface. This range is selected in the
LPC_Sound Decode Range Register.
SB16_LPC_ENâR/W.
4
0 = Disable.
1 = Enables the decoding of the SB16 range to the LPC interface. This range is selected in the
LPC_Sound Decode Range Register.
FDD_LPC_ENâR/W.
3
0 = Disable.
1 = Enables the decoding of the FDD range to the LPC interface. This range is selected in the
LPC_FDD/LPT Decode Range Register.
LPT_LPC_ENâR/W.
2
0 = Disable.
1 = Enables the decoding of the LPTrange to the LPC interface. This range is selected in the
LPC_FDD/LPT Decode Range Register.
COMB_LPC_ENâR/W.
1
0 = Disable.
1 = Enables the decoding of the COMB range to the LPC interface. This range is selected in the
LPC_COM Decode Range Register.
COMA_LPC_ENâR/W.
0
0 = Disable.
1 = Enables the decoding of the COMA range to the LPC interface. This range is selected in the
LPC_COM Decode Range Register.
Intel® 82801CA ICH3-S Datasheet
293
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