82801CA Datasheet, PDF (395/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

USB 1.1 Controllers Registers
11.2.5
11.2.6
FRBASEADD—Frame List Base Address Register
I/O Offset:
Default Value:
Base + (08–0Bh)
Undefined
Attribute:
Size:
R/W
32 bits
This 32-bit register contains the beginning address of the Frame List in the system memory. HCD
loads this register prior to starting the schedule execution by the Host Controller. When written,
only the upper 20 bits are used. The lower 12 bits are written as zero (4-KB alignment). The
contents of this register are combined with the frame number counter to enable the Host Controller
to step through the Frame List in sequence. The two least significant bits are always 00. This
requires DWord alignment for all list entries. This configuration supports 1024 Frame List entries.
Bit
Description
31:12 Base Address—R/W. These bits correspond to memory address signals [31:12], respectively.
11:0 Reserved.
SOFMOD—Start of Frame Modify Register
I/O Offset:
Default Value:
Base + (0Ch)
40h
Attribute:
Size:
R/W
8 bits
This 1-byte register is used to modify the value used in the generation of SOF timing on the USB.
Only the 7 least significant bits are used. When a new value is written into these 7 bits, the SOF
timing of the next frame will be adjusted. This feature can be used to adjust out any offset from the
clock source that generates the clock that drives the SOF counter. This register can also be used to
maintain real time synchronization with the rest of the system so that all devices have the same
sense of real time. Using this register, the frame length can be adjusted across the full range
required by the USB specification. It’s initial programmed value is system dependent based on the
accuracy of hardware USB clock and is initialized by system BIOS. It may be reprogrammed by
USB system software at any time. Its value will take effect from the beginning of the next frame.
This register is reset upon a Host Controller Reset or Global Reset. Software must maintain a copy
of its value for reprogramming if necessary.
Bit
Description
7 Reserved.
SOF Timing Value—R/W. Guidelines for the modification of frame time are contained in Chapter 7 of
the USB Specification. The SOF cycle time (number of SOF counter clock periods to generate a SOF
frame length) is equal to 11936 + value in this field. The default value is decimal 64 which gives a SOF
cycle time of 12000. For a 12 MHz SOF counter clock input, this produces a 1 ms Frame period. The
following table indicates what SOF Timing Value to program into this field for a certain frame period.
Frame Length
(# 12 MHz Clocks)
(decimal)
SOF Reg. Value
(decimal)
11936
0
6:0
11937
1
.
.
.
.
11999
63
12000
64
12001
65
.
.
.
.
12062
126
12063
127
Intel^® 82801CA ICH3-S Datasheet
395