82801CA Datasheet, PDF (286/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.1.22
GEN_CNTL—General Control Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
D0h–D3h
00000000h
No
Attribute:
Size:
Power Well:
R/W
32-bit
Core
Bit
Description
31:26
25
24
23: 22
21
20:14
13
12
11
10:9
8
Reserved.
REQ[5]#/GNT[5]# PC/PCI Protocol Select (PCPCIB_SEL)—R/W.
0 = The REQ[5]#/GNT[5]# pins will function as a standard PCI REQ/GNT signal pair.
1 = When this bit is set to a 1, the PCI REQ[5]#/GNT[5]# signal pair will use the PC/PCI protocol as
REQ[B]#/GNT[B]. The corresponding bits in the GPIO_USE_SEL register must also be set to a
0. If the corresponding bits in the GPIO_USE_SEL register are set to a 1, then the signals will
be used as a GPI and GPO.
Hide ISA Bridge (HIDE_ISA)—R/W.
The ICH3 will not prevent AD22 from asserting during configuration cycles to the PCI-to-ISA bridge.
1 = Software sets this bit to 1 to disable configuration cycle from being claimed by a PCI-to-ISA
bridge. This will prevent the OS PCI PnP from getting confused by seeing two ISA bridges.
It is required for the ICH3 PCI address line AD22 to connect to the PCI-to-ISA bridge’s IDSEL
input. When this bit is set, the ICH3 will not assert AD22 during configuration cycles to the PCI-
to-ISA bridge.
Reserved.
Processor Break Event Indication Enable (FERR#-MUX-EN)—R/W.
0 = (Default) The ICH3 will not examine the FERR# signal during C2.
1 = Software sets this bit to 1 to enable the ICH3 to examine the FERR# signal during a C2 state as
a break event. (see Section 6.12.6 for details).
Reserved.
Coprocessor Error Enable (COPR_ERR_EN)—R/W.
0 = FERR# will not generate IRQ13 nor IGNNE#.
1 = When FERR# is low, ICH3 generates IRQ13 internally and holds it until an I/O write to port F0h.
It will also drive IGNNE# active.
Keyboard IRQ1 Latch Enable (IRQ1LEN)—R/W.
0 = IRQ1 will bypass the latch.
1 = The active edge of IRQ1 will be latched and held until a port 60h read.
Mouse IRQ12 Latch Enable (IRQ12LEN)—R/W.
0 = IRQ12 will bypass the latch.
1 = The active edge of IRQ12 will be latched and held until a port 60h read.
Reserved.
APIC Enable (APIC_EN)—R/W.
0 = Disables internal I/O (x) APIC.
1 = Enables the internal I/O (x) APIC and its address decode.
The following behavioral rules apply for bits 8 and 7 in this register:
Rule 1: If bit 8 is 0, then the ICH3 will not decode any of the registers associated with the I/O APIC
or I/O (x) APIC. The state of bit 7 is “Don’t Care” in this case.
Rule 2: If bit 8 is 1 and bit 7 is 0, then the ICH3 will decode the memory space associated with the I/
O APIC, but not the extra registers associated I/O (x) APIC.
Rule 3: If bit 8 is 1 and bit 7 is 1, then the ICH3 will decode the memory space associated with both
the I/O APIC and the I/O (x) APIC. This also enables PCI masters to write directly to the register to
cause interrupts (PCI Message Interrupt).
NOTE: There is no separate way to disable PCI Message Interrupts if the I/O (x) APIC is enabled.
This is not considered necessary.
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Intel^® 82801CA ICH3-S Datasheet