82801CA Datasheet, PDF (239/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LAN Controller Registers (B1:D8:F0)
7.1.10 HEADTYP—Header Type Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Eh
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7 Multi-Function Device—RO. Hardwired to 0 to indicate a single function device.
6:0
Header Type—RO. 7-bit field identifies the header layout of the configuration space as an Ethernet
controller.
7.1.11 CSR_MEM_BASE CSR—Memory-Mapped Base Address
Register (LAN Controller—B1:D8:F0)
Offset Address: 10–13h
Default Value: 0000 0008h
Attribute:
Size:
R/W, RO
32 bits
Note: The ICH3’s integrated LAN Controller requires one BAR for memory mapping. Software
determines which BAR (memory or I/O) is used to access the Lan Controller’s CSR registers.
Bit
Description
31:12
Base Address—R/W. Upper 20 bits of the base address provides 4 KB of memory-Mapped space for
the LAN Controller’s Control/Status Registers.
11:4 Reserved.
3
Prefetchable—RO. Hardwired to 0 to indicate that this is not a pre-fetchable memory-Mapped
address range.
2:1
Type—RO. Hardwired to 00b to indicate the memory-Mapped address range may be located
anywhere in 32-bit address space.
0
Memory Space Indicator—RO. Hardwired to 0 to indicate that this base address maps to memory
space.
7.1.12 CSR_IO_BASE—CSR I/O-Mapped Base Address Register
(LAN Controller—B1:D8:F0)
Offset Address: 14–17h
Default Value: 0000 0001h
Attribute:
Size:
R/W
32 bits
Note: The ICH3’s integrated LAN Controller requires one BAR for memory mapping. Software
determines which BAR (memory or I/O) is used to access the Lan Controller’s CSR registers.
Bit
Description
31:16 Reserved.
15:6
Base Address—R/W. Provides 64 bytes of I/O-Mapped address space for the LAN Controller’s
Control/Status Registers.
5:1 Reserved.
0 I/O Space Indicator—RO. Hardwired to 1 to indicate that this base address maps to I/O space.
Intel^® 82801CA ICH3-S Datasheet
239