82801CA Datasheet, PDF (202/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
after receiving data byte N–1 of the block, the software needs to set the LAST_BYTE bit in the
Host Control Register; this allows the ICH3 to send a NOT ACK (instead of an ACK) after
receiving the last data byte (byte N) of the block.
After each byte of a block message the ICH3 sets the BYTE_DONE_STS bit and generates an
interrupt or SMI#. Software clears the BYTE_DONE_STS bit before the next transfer occurs.
When the interrupt handler clears the BYTE_DONE_STS bit after the last byte has been
transferred, the ICH3 will set the INTR bit and generate another interrupt to signal the end of the
block transfer. Thus, for a block message of n bytes, the ICH3 will generate n+1 interrupts. The
interrupt handler needs to be implemented to handle all of these interrupts.
The format of the Block Read/Write protocol is shown in Table 5-86 and Table 5-87.
Note: For Block Write, if the I²C_EN bit is set, the format of the command changes slightly. The ICH3
will still send the number of bytes indicated in the Data 0 Register. However, it will not send the
contents of the Data 0 Register as part of the message. The Block Write command with I2C_EN set
and the PEC_EN bit set produces undefined results. Software must force the PEC_EN bit to 0
when running this command.
l
Table 5-86. Block Read/Write Protocol without PEC
Block Write Protocol
Block Read Protocol
Bit
1
2–8
9
10
11–18
19
20–27
28
29–36
37
38–45
46
...
...
...
...
Description
Start
Slave Address–7 bits
Write
Acknowledge from slave
Command code–8 bits
Acknowledge from slave
Byte Count–8 bits
(Skip this step if I2C_EN bit set)
Acknowledge from Slave
(Skip this step if I2C_EN bit set)
Data Byte 1–8 bits
Acknowledge from Slave
Data Byte 2–8 bits
Acknowledge from slave
Data Bytes / Slave
Acknowledges...
Data Byte N–8 bits
Acknowledge from Slave
Stop
Bit
1
2–8
9
10
11–18
19
20
Description
Start
Slave Address–7 bits
Write
Acknowledge from slave
Command code–8 bits
Acknowledge from slave
Repeated Start
21–27
28
29
30–37
38
39–46
47
48–55
56
...
...
...
...
Slave Address–7 bits
Read
Acknowledge from slave
Byte Count from slave–8 bits
Acknowledge
Data Byte 1 from slave–8 bits
Acknowledge
Data Byte 2 from slave–8 bits
Acknowledge
Data Bytes from slave/Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
Stop
202
Intel^® 82801CA ICH3-S Datasheet