82801CA Datasheet, PDF (368/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

IDE Controller Registers (D31:F1)
10.1.6
10.1.7
10.1.8
10.1.9
PI—Programming Interface Register (IDE—D31:F1)
Address Offset: 09h
Default Value: 8Ah
Attribute:
Size:
R/W
8 bits
Bit
Description
7 This read-only bit is a 1 to indicate that the ICH3 supports bus master operation.
6:4 Reserved. Will always return 0.
3
SOP_MODE_CAP. This read-only bit is a 1 to indicate that the secondary controller supports both
legacy and native modes.
SOP_MODE_SEL. This read-write bits determines the mode that the secondary IDE channel is
operating in.
2
0 = Legacy-PCI mode (default).
1 = Native-PCI mode.
1
POP_MODE_CAP. This read-only bit is a 1 to indicate that the primary controller supports both
legacy and native modes.
POP_MODE_SEL. This read-write bits determines the mode that the primary IDE channel is
operating in.
0
0 = Legacy-PCI mode (default).
1 = Native-PCI mode.
SCC—Sub Class Code Register (IDE—D31:F1)
Address Offset: 0Ah
Default Value: 01h
Attribute:
Size:
RO
8 bits
Bit
Description
Sub Class Code—RO.
7:0
01h = IDE device, in the context of a mass storage device.
BCC—Base Class Code Register (IDE—D31:F1)
Address Offset: 0Bh
Default Value: 01h
Attribute:
Size:
RO
8 bits
Bit
Base Class Code—RO.
7:0
01 = Mass storage device.
Description
MLT—Master Latency Timer Register (IDE—D31:F1)
Address Offset: 0Dh
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Master Latency Timer Count (MLTC)—RO. Hardwired to 00h. The IDE controller is implemented
internally, and is not arbitrated as a PCI device, so it does not need a Master Latency Timer.
368
Intel^® 82801CA ICH3-S Datasheet