82801CA Datasheet, PDF (59/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Power Planes and Pin States
Table 3-4. Power Plane and States for Output and I/O Signal (Continued)
Signal Name
Power
Plane
During
PCIRST#⁴ /
RSMRST#⁵
Immediately
after
PCIRST#⁴ /
RSMRST#⁵
S1
A20M#
CPUPWRGD
CPUSLP#
IGNNE#
INIT#
INTR
NMI
SMI#
STPCLK#
SMBCLK, SMBDATA
SMLINK[1:0]
SPKR
AC_RST#
AC_SDOUT
AC_SYNC
GPIO[18]
GPIO[19:20]
GPIO[21]
GPIO[22]
GPIO[23]
GPIO[24]
GPIO[25]
GPIO[27:28]
GPIO[43:32]
CPU Interface
CPU I/O
Main I/O
CPU I/O
CPU I/O
CPU I/O
CPU I/O
CPU I/O
CPU I/O
CPU I/O
See Note 1
See Note 3
High
See Note 1
High
See Note 1
See Note 1
High
High
High
High-Z
High
High
High
Low
Low
High
High
High
High-Z
Defined
High
High
Low
Low
High
Low
SMBus Interface
Resume I/O High-Z
High-Z
Defined
System Management Interface
Resume I/O High-Z
High-Z
Defined
Miscellaneous Signals
Low with
Main I/O internal pull-
Low
down
Defined
AC’97 Interface
Resume I/O
Low
Main I/O
Low
Main I/O
Low
Low
Running
Running
Cold Reset
Bit (High)
Low
Low
Unmuxed GPIO Signals
Main I/O
Main I/O
Main I/O
Main I/O
Main I/O
Resume I/O
Resume I/O
Resume I/O
Main I/O
High
High
High
High-Z
Low
Low
High
High
High
See Note 2
High
High
High-Z
Low
Low
High
High
High
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Defined
S3
Off
Off
Off
Off
Off
Off
Off
Off
Off
Defined
Defined
Off
Low
Off
Off
Off
Off
Off
Off
Off
Defined
Defined
Defined
Off
S4/S5
Off
Off
Off
Off
Off
Off
Off
Off
Off
Defined
Defined
Off
Low
Off
Off
Off
Off
Off
Off
Off
Defined
Defined
Defined
Off
NOTES:
1. ICH3 sets these signals at reset for CPU frequency strap.
2. GPIO[18] will toggle at a frequency of approximately 1Hz when the ICH3 comes out of reset
3. CPUPWRGD is an open-drain output that represents a logical AND of the ICH3’s VRMPWRGD and PWROK
signals, and thus will be driven low by ICH3 when either VRMPWRGD or PWROK are inactive. During boot,
or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low to High-Z.
4. The states of main I/O signals are taken at the times During PCIRST# and Immediately after PCIRST#.
5. The states of resume I/O signals are taken at the times During RSMRST# and Immediately after RSMRST#
.
Intel^® 82801CA ICH3-S Datasheet
3-59