82801CA Datasheet, PDF (389/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

USB 1.1 Controllers Registers
11.2 USB I/O Registers
Some of the read/write register bits which deal with changing the state of the USB hub ports
function such that on read back they reflect the current state of the port, and not necessarily the
state of the last write to the register. This allows the software to poll the state of the port and wait
until it is in the proper state before proceeding. A Host Controller Reset, Global Reset, or Port
Reset will immediately terminate a transfer on the affected ports and disable the port. This affects
the USBCMD register, bit [4] and the PORTSC registers, bits [12,6,2]. See individual bit
descriptions for more detail.
Table 11-2. USB I/O Registers
Offset
00–01h
02–03h
04–05h
06–07h
08–0Bh
0Ch
0D–0Fh
10–11h
12–13h
14–17h
18h
Mnemonic
Register
USBCMD USB Command
USBSTS USB Status
USBINTR USB Interrupt Enable
FRNUM
USB Frame Number
FRBASEADD USB Frame List Base Address
SOFMOD
—
PORTSC0
PORTSC1
USB Start of Frame Modify
Reserved
Port 0 Status/Control
Port 1 Status/Control
—
Reserved
LOOPDATA Loop Back Test Data
Default
0000h
0020h
0000h
0000h
Undefined
40h
0
0080h
0080h
0
00h
Type
R/W*
R/WC
R/W
R/W (see Note 1)
R/W
R/W
RO
R/WC (see Note 1)
R/WC (see Note 1)
RO
RO
NOTES:
1. These registers are WORD writable only. Byte writes to these registers have unpredictable effects.
Intel^® 82801CA ICH3-S Datasheet
389