82801CA Datasheet, PDF (236/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LAN Controller Registers (B1:D8:F0)
7.1.1
7.1.2
7.1.3
236
VID—Vendor ID Register (LAN Controller—B1:D8:F0)
Offset Address: 00–01h
Default Value: 8086h
Attribute:
Size:
RO
16 bits
Bit
Description
15:0 Vendor Identification Value. This is a 16-bit value assigned to Intel.
DID—Device ID Register (LAN Controller—B1:D8:F0)
Offset Address: 02–03h
Default Value: 2449h
Attribute:
Size:
RO
16 bits
Bit
Description
Device Identification Value. This is a 16-bit value assigned to the ICH3 integrated LAN Controller.
1. If the EEPROM is not present (or not properly programmed), reads to the Device ID return the
15:0
default value of 2449h.
2. If the EEPROM is present (or properly programmed) and if the value of Word 23h is not 0000f
or FFFFh, the Device ID is loaded from the EEPROM, Word 23h after the hardware reset.
(See Section 7.1.14–SID, Subsystem ID of LAN controller for detail).
PCICMD—PCI Command Register
(LAN Controller—B1:D8:F0)
Offset Address: 04–05h
Default Value: 0000h
Attribute:
Size:
RO, R/W
16 bits
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Description
Reserved.
Fast Back to Back Enable (FBE)—RO. Hardwired to 0. The integrated LAN Controller will not run
fast back-to-back PCI cycles.
SERR# Enable (SERR_EN)—R/W.
0 = Disable.
1 = Enable. Allow SERR# to be asserted.
Wait Cycle Control (WCC)—RO. Hardwired to 0. Not implemented.
Parity Error Response (PER)—R/W.
0 = The LAN Controller will ignore PCI parity errors.
1 = The integrated LAN Controller will take normal action when a PCI parity error is detected and
will enable generation of parity on the hub interface.
VGA Palette Snoop (VPS)—RO. Hardwired to 0’. Not Implemented.
Memory Write and Invalidate Enable (MWIE)—R/W.
0 = Disable. The LAN Controller will not use the Memory Write and Invalidate command.
1 = Enable.
Special Cycle Enable (SCE)—RO. Hardwired to 0. The LAN Controller ignores special cycles.
Bus Master Enable (BME)—R/W.
0 = Disable.
1 = Enable. The ICH3’s integrated may function as a PCI bus master.
Memory Space Enable (MSE)—R/W.
0 = Disable.
1 = Enable. The ICH3’s integrated LAN Controller will respond to the memory space accesses.
I/O Space Enable (IOE)—R/W.
0 = Disable.
1 = Enable. The ICH3’s integrated LAN Controller will respond to the I/O space accesses.
Intel^® 82801CA ICH3-S Datasheet