82801CA Datasheet, PDF (363/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.10.7
9.10.8
9.10.9
GPIO_USE_SEL2—GPIO Use Select 2 Register
Offset Address:
Default Value:
Lockable:
GPIOBASE +30h
00000000h
No
Attribute:
Size:
Power Well:
R/W
32-bit
Core
Bit
Description
GPIO_USE_SEL2[43:32]—R/W. Each bit in this register enables the corresponding GPIO
(if it exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
31:0
NOTES:
1. Bits 31:12 are not implemented because they have no corresponding GPIOs.
2. If GPIO[n] does not exist, the bit in this register always reads as 0 and writes have no
effect.
After a full reset (RSMRST#) all multiplexed signals in the resume and core wells are
configured as their native function rather than as a GPIO. After just a PCIRST#, the GPIO in
the core well are configured as their native function.
GP_IO_SEL2—GPIO Input/Output Select 2 Register
Offset Address:
Default Value:
Lockable:
GPIOBASE +34h
00000000h
No
Attribute:
Size:
Power Well:
R/W
32-bit
Core
Bit
31:12
11:0
Description
Always 0. No corresponding GPIO.
GP_IO_SEL2[43:32]. When set to a 1, the corresponding GPIO signal (if enabled in the
GPIO_USE_SEL2 register) is programmed as an input. When set to 0, the GPIO signal is
programmed as an output.
GP_LVL2—GPIO Level for Input or Output 2 Register
Offset Address:
Default Value:
Lockable:
GPIOBASE +38h
00000FFFh
No
Attribute:
Size:
Power Well:
R/W
32-bit
See below
Bit
31:12
11:0
Description
Reserved. Read-only 0.
GP_LVL2[43:32]. If GPIO[n] is programmed to be an output (via the corresponding bit in the
GP_IO_SEL2 register), then the corresponding GP_LVL2[n] bit can be updated by software
to drive a high or low value on the output pin. 1 = high, 0 = low. If GPIO[n] is programmed as
an input, then the corresponding GP_LVL2 bit reflects the state of the input signal
(1 = high, 0 = low). Writes will have no effect.
Since these bits correspond to GPIO that are in the core well, these bits will be reset by
PCIRST#.
Intel^® 82801CA ICH3-S Datasheet
363