82801CA Datasheet, PDF (507/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Register Index
Table A-2. Intel^® ICH3 Fixed I/O Registers (Continued)
Register Name
Channel 4–7 DMA Write All Mask
Register
Aliased at DEh
Coprocessor Error Reigster
PIO Mode Command Block Offset
for Secondary Drive
PIO Mode Command Block Offset
for Primary Drive
PIO Mode Control Block Offset for
Secondary Drive
PIO Mode Control Block Offset for
Primary Drive
Master PIC Edge/Level Triggered
Register
Slave PIC Edge/Level Triggered
Register
Reset Control Register
Port
DEh
DFh
F0h
Datasheet Section and Location
Section 9.2.11, “DMA_WRMSK—DMA Write All Mask
Register” on page 9-304
Section 9.7.4, “COPROC_ERR—Coprocessor Error
Register” on page 9-328
170–177h See ATA Specification for detailed register description
1F0–1F7h See ATA Specification for detailed register description
376h
See ATA Specification for detailed register description
3F6h
4D0h
4D1h
CF9h
See ATA Specification for detailed register description
Section 9.4.10, “ELCR1—Master Controller Edge/Level
Triggered Register” on page 9-314
Section 9.4.11, “ELCR2—Slave Controller Edge/Level
Triggered Register” on page 9-315
Section 9.7.5, “RST_CNT—Reset Control Register” on
page 9-329
NOTE: When the POS_DEC_EN bit is set, additional I/O ports get positively decoded by the ICH3.
Intel^® 82801CA ICH3-S Datasheet
507