82801CA Datasheet, PDF (342/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.8.3.6
LV2—Level 2 Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 14h
(ACPI P_BLK+4)
00h
No
Core
Attribute:
Size:
Usage:
RO
8-bit
ACPI or Legacy
Bit
Description
Reads to this register return all zeros, writes to this register have no effect. Reads to this register
7:0
generate a “enter a level 2 power state” (C2) to the clock control logic. This will cause the STPCLK#
signal to go active, and stay active until a break event occurs. Throttling (due either to THTL_EN or
THRM# override) will be ignored.
9.8.3.7
GPE0_STS—General Purpose Event 0 Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 28h
(ACPI GPE0_BLK)
0000h
No
Resume
Attribute:
Size:
Usage:
R/WC
16-bit
ACPI
Note:
This register is symmetrical to the General Purpose Event 0 Enable Register. If the corresponding
_EN bit is set, then when the _STS bit get set, the ICH3 generates a Wake Event. Once back in an
S0 state (or if already in an S0 state when the event occurs), the ICH3 also generates an SCI if the
SCI_EN bit is set, or an SMI# if the SCI_EN bit is not set. There will be no SCI/SMI# or wake
event on THRMOR_STS since there is no corresponding _EN bit. None of these bits are reset by
CF9h write. All are reset by RSMRST#.
Bit
15:14
13
12
11
10:9
Description
Reserved.
PME_B0_STS—R/W.
0 = The default for this bit is 0. Writing a 1 to this bit clears this bit.
1 = Set to 1 by the ICH3 when any internal device on bus 0 asserts the equivalent of the PME#
signal. Additionally, if the PME_B0_EN bit is set and the system is in an S0 state, the setting
of the PME_B0_STS bit generates an SCI (or SMI# if SCI_EN is not set). If the
PME_B0_STS bit is set and the system is in an S1–S4 state (or S5 state due to SLP_TYP
and SLP_EN), the setting of the PME_B0_STS bit generates a wake event, and an SCI (or
SMI# if SCI_EN is not set) is generated. If the system is in an S5 state due to power button
override, the PME_B0_STS bit does not cause a wake event or SCI.
USB3_STS—R/W
0 = Disable.
1 = Set by hardware and can be reset by writing a one to this bit position or a resume-well reset.
This bit is set when USB 1.1 Controller #3 needs to cause a wake. Additionally if the
USB3_EN bit is set, the setting of the USB3_STS bit will generate a wake event.
PME_STS—R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN bit is set,
and the system is in an S0 state, then the setting of the PME_STS bit will generate an SCI or
SMI# (if SCI_EN is not set). If the PME_EN bit is set, and the system is in an S1-S4 state (or
S5 state due to setting SLP_TYP and SLP_EN), then the setting of the PME_STS bit will
generate a wake event, and an SCI will be generated. If the system is in an S5 state due to
power button override or a power failure, then PME_STS will not cause a wake event or SCI.
Reserved.
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Intel^® 82801CA ICH3-S Datasheet