82801CA Datasheet, PDF (276/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
Table 9-1. PCI Configuration Map (LPC I/F—D31:F0) (Continued)
Offset
E0h
E1h
E2h
E3h
E4–E5h
E6–E7h
E8–EBh
EC–EDh
EE–EFh
F0h
F2h
Mnemonic
Register Name
COM_DEC LPC I/F COM Port Decode Ranges
LPCFDD_DEC LPC I/F FDD & LPT Decode Ranges
SND_DEC
LPC I/F Sound Decode Ranges
FWH_DEC_EN1 FWH Decode Enable 1
GEN1_DEC LPC I/F General 1 Decode Range
LPC_EN
FWH_SEL1
GEN2_DEC
FWH_SEL2
LPC I/F Enables
FWH Select 1
LPC I/F General 2 Decode Range
FWH Select 2
FWH_DEC_EN2 FWH Decode Enable 2
FUNC_DIS Function Disable
NOTE 1:Refer to the Specification Update for the Revision ID.
Default
00h
00h
00h
FFh
0000h
00h
00112233h
0000h
5678h
0Fh
00h
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
9.1.1
VID—Vendor ID Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
00–01h
8086h
No
Attribute:
Size:
Power Well:
RO
16-bit
Core
Bit
Description
15:0 Vendor Identification Value. This is a 16 bit value assigned to Intel. Intel VID = 8086h.
9.1.2
DID—Device ID Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
02–03h
2480h
No
Attribute:
Size:
Power Well:
RO
16-bit
Core
Bit
Description
15:0 Device Identification Value. This is a 16 bit value assigned to the ICH3 LPC Bridge.
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Intel^® 82801CA ICH3-S Datasheet