82801CA Datasheet, PDF (180/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.16.2.3 Command Register, Status Register, and TD Status Bit Interaction
Table 5-65. Command Register, Status Register and TD Status Bit Interaction
Condition
ICH3 USB Status Register Actions
CRC/Time Out Error Set USB Error Int bit¹, Clear HC Halted bit
Illegal PID, PID Error,
Max Length (illegal)
Clear Run/Stop bit in command register
Set HC Process Error and HC Halted bits
PCI Master/Target
Abort
Suspend Mode
Clear Run/Stop bit in command register
Set Host System Error and HC Halted bits
Clear Run/Stop bit in command register²
Set HC Halted bit
Resume Received and
Set Resume received bit
Suspend Mode = 1
Run/Stop = 0
Clear Run/Stop bit in command register
Set HC Halted bit
Configuration Flag Set Set Configuration Flag in command register
HC Reset/Global Reset
Clear Run/Stop and Configuration Flag in
command register
Clear USB Int, USB Error Int, Resume received,
Host System Error, HC Process Error, and HC
Halted bits
IOC = 1 in TD Status Set USB Int bit
Stall
Set USB Error Int bit
Bit Stuff/Data Buffer
Error
Set USB Error Int bit¹
Short Packet Detect Set USB Int bit
TD Status Register Actions
Clear Active bit¹ and set Stall
bit¹
Clear Active bit¹ and set Stall bit
Clear Active bit¹ and set Stall
bit¹
Clear Active bit
NOTES:
1. Only If error counter counted down from 1 to 0
2. Suspend mode can be entered only when Run/Stop bit is 0
Note that if a NAK or STALL response is received from a SETUP transaction, a Time Out Error
will be reported. This will cause the Error counter to decrement and the CRC/Time-out Error status
bit to be set within the TD Control and Status dword during write back. If the Error counter
changes from 1 to 0, the Active bit will be reset to 0 and Stalled bit to 1 as normal.
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Intel^® 82801CA ICH3-S Datasheet